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參數(shù)資料
| 型號： | STLC7550TQFP |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW POWER LOW VOLTAGE ANALOG FRONT END |
| 中文描述： | 低電壓低功耗模擬前端 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大小： | 174K |
| 代理商： | STLC7550TQFP |
Bit 3-4-5
Internal
Sampling
M/S
Sync
FS
SCLK
(OCLK)
% OVER
XTALIN
(MCLK)
XTALOUT
÷ M
÷ Q
MCM
Cont. Reg. : Bit 8-9-10-11-12-13
V
DD
7
Figure 1 :
Clock Block Diagram
FUNCTIONAL DESCRIPTION
(continued)
4 - MODES OF OPERATION
Thanks to MCM and M/S programmation pins we
can get the following configuration.
Configuration 1 :
MCM = 1, M/S = 1
The STLC7550 is in master mode and we have :
Fs = XTAL IN / (M x Q x OVER)
Fs and SCLK are output pins.
SCLK
FS
DIN
DOUT
BCLK
FS
DO
DI
XTALIN
M/S
MCM
STLC7550
PROCESSOR
V
DD
V
DD
f
Q
= 36.864MHz
TS
GND
7
Figure 2 :
Configuration 1
SCLK
FS
DIN
DOUT
XTALIN
M/S
MCM
STLC7550
V
DD
GND
f
Q
= K x Fs
BCLK
FS
DO
DI
PROCESSOR
TS
GND
7
Figure 4 :
Configuration 3 (7546 mode)
SCLK
FS
DIN
DOUT
BCLK
FS
DO
DI
XTALIN
M/S
MCM
STLC7550
PROCESSOR
GND
V
DD
f
Q
= 36.864MHz
TS
GND
7
Figure 3 :
Configuration 2
Configuration 2 :
MCM = 1, M/S = 0
The STLC7550 is in slave mode. SCLK is provided
by the STLC7550, the processor generates the Fs
and controls the phase of the sampling frequency.
Fs must be the result of a division of a number of
cycles of SLCK (Fs = SCLK % OVER).
Configuration 3 :
MCM = 0, M/S = 1
The STLC7550 is in master mode and the proces-
sor provides the XTAL IN = MCLK = OCLK.
The STLC7550 generates the Fs from OCLK. In
this mode the configuration 3 is equivalent to the
STLC7546 mode.
Configuration 4 :
MCM = 0, M/S = 0
The STLC7550 is in slave mode.
The configuration 4 is equivalent to configuration 3
but the Fs is generated and phase controlled by the
processor.
Configuration 5 :
MCM = 1, M/S = 1 (master codec)
MCM = 0, M/S = 0 (slave codec)
This is dual codec application.
The master codec has his data in timeslot 0 and
the slave codec has his data in timeslot 1 thanks to
the programmation of TS.
STLC7550
7/17
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