參數(shù)資料
型號(hào)： STLC7550
廠商： 意法半導(dǎo)體
英文描述： LOW POWER LOW VOLTAGE ANALOG FRONT END
中文描述： 低電壓低功耗模擬前端
文件頁(yè)數(shù)： 6/17頁(yè)
文件大?。?/td> 174K
代理商： STLC7550
FUNCTIONAL DESCRIPTION
1 - TRANSMIT D/A SECTION
The functions included in the Tx D/A section are
detailed hereafter. 16-bit 2’s complement data for-
mat is used in the DAC channel.
1.1 - Transmit Low Pass Filters
The transmit low pass filter is basically an interpo-
lating filter including a sinx/x correction. It is a
combination of Finite Impulse Response filter (FIR)
and an Infinite Impulse Response filter (IIR). The
digital signal from the serial interface gets interpo-
lated by 2, 3, 4, 5 or 6 x Sampling Frequency (FS)
through the IIR filter. The signal is further interpo-
lated by 32 x FS x n (with n equal to 2, 3, 4, 5, 6)
through the IIR and FIR filter. The low pass filter is
followed by the DAC. The DAC is oversampled at
64, 96, 128, 160, 192 x FS. The oversampling ratio
is user selectable.
1.2 - D/A Converter
The oversampled D/A converter includes a second
order digital noise shaper, a one bit D/A converter
and a single pole analog low-pass filter.
The attenuation of the last output stage can be
programmed to 0dB, +6dB or infinite. The cut-off
frequency of the single pole switch-capacitor low-
pass filter is :
fc
3dB
=
OCLK
2
π
10
with OCLK = Oversampling Clock frequency.
Continuous-time filtering of the analog differential
output is necessary using an off-chip amplifier and
a few external passive components.
At least 79dB signal to noise plus distortion ratio can
be obtained in the frequency band of 0.425 x 9.6kHz
(with an oversampling ratio equal to 160).
2 - RECEIVE A/D SECTION
The different functions included in the ADC channel
section are described below. 16-bit 2’s complement
data format is used in the ADC.
2.1 - A/D Converter
The oversampled A/D converter is based on a
second order sigma-delta modulator. To produce
excellent common-mode rejection of unwanted sig-
nals, the analog signal is processed differentially
until it is converted to digital data. Single-ended
mode can also be used. The ADC is oversampled
at 64, 96, 128, 160 or 192 x FS. The oversampling
ratio is user selectable. At least -85dB SNDR can
be expected in the 0.425 x 9.6kHz bandwidth with
a -6dBr differential input signal and an oversam-
pling ratio equal to 160.
2.2 - Receive Low Pass Filter
It is a decimation filter. The decimation is performed
by two decimation digital filters : one decimation
FIR filter and one decimation IIR filter.
The purpose of the FIR filter is to decimate 32 times
the digital signal coming from the ADC modulator.
The IIR is a cascade of 5 biquads. It provides the
low-pass filtering needed to remove the noise re-
maining above half the sampling frequency. The
output of the IIR will be processed by the DSP.
3 - CLOCK GENERATOR
The master clock, MCLK is provided by the user
thanks to a crystal or external clock generator (see
Figure 1).
The MCLK could be equal to 36.864MHz
(MCM = 1). In that case thanks to the divider M x Q,
the STLC7550 is able to generate all V.34bis and
56 Kbps sampling frequencies (see Table 1).
When MCM = 0, the MCLK must be equal to the
oversampling frequency : Fs x OVER (7546 mode).
The ADC and DAC are oversampled at the OCLK
frequency. OCLK is equal to the shift clock used in
the serial interface.
The MCLK frequency should be :
MCLK = K x Sampling frequency
Combination of M, Q and oversampling ratios al-
lows to generate several sampling frequencies.
Recommended values for classical modem appli-
cations are as follow :
Table 1 :
Sampling Frequencies Generation
F
(kHz)
FQ =
36.864MHz (1)
M
Q
3
6
3
5.5
3
7
3
6
3
8
3
6.5
3
7
4
5.5
4
7
4
6
4
8
4
6.5
4
7
4
6
4
8
FQ =
18.432MHz
M
Q
2
4.5
-
-
1
7
2
4.5
2
6
-
-
-
-
2
5.5
2
7
2
6
2
8
2
6.5
2
7
2
6
2
8
FQ =
9.216MHz
Q
6
-
7
4.5
6
-
-
5.5
7
6
8
6.5
7
6
8
over
128
160
128
160
128
160
160
160
128
160
128
160
160
192
160
over M
128
-
192
160
128
-
-
160
128
160
128
160
160
192
160
over
96
-
96
160
128
-
-
160
128
160
128
160
160
192
160
16.00
13.96
13.71
12.80
12.00
11.82
10.97
10.47
10.29
9.60
9.00
8.86
8.23
8.00
7.20
1
-
1
1
1
-
-
1
1
1
1
1
1
1
1
Note :
1. Recommended value.
STLC7550
6/17
相關(guān)PDF資料
PDF描述
STLC8100 DUAL BAND WIRELESS LAN RF TRANSCEIVER
STLIB4HDS Development Environment For ST16 and ST19 Smartcard MCU Families
ST16-19HDSE Development Environment For ST16 and ST19 Smartcard MCU Families
ST16-19 Pulse Width Modulation (PWM) Controller IC; Topology:Buck (Step Down); Control Mode:Current, Voltage; Number of PWM Outputs:2; Input Voltage Primary Min:3V; Input Voltage Primary Max:6.5V; Oscillator Frequency Max, Fosc:2MHz
ST16-19RFRDCS CHIP SET INTERFACE SPECIFICATION
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
STLC7550TQF7 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
STLC7550TQF7TR 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
STLC7550TQFP 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:LOW POWER LOW VOLTAGE ANALOG FRONT END
STLC75C53TQFP 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MODEM
STLC8100 制造商:STMicroelectronics 功能描述:RF TRNSCVR 5GHZ 48TQFP - Trays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*