- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380765 > STLC7550 (意法半導(dǎo)體) LOW POWER LOW VOLTAGE ANALOG FRONT END PDF資料下載
參數(shù)資料
| 型號(hào)： | STLC7550 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW POWER LOW VOLTAGE ANALOG FRONT END |
| 中文描述： | 低電壓低功耗模擬前端 |
| 文件頁(yè)數(shù)： | 15/17頁(yè) |
| 文件大?。?/td> | 174K |
| 代理商： | STLC7550 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)第17頁(yè)
DEFINITION AND TERMINOLOGY
Data Transfer Interval
The time during which data is transfered from D
OUT
and to D
IN
. This
interval is 16 shift clocks provides by the chip.
This refers to the input signal and all the converted representations
through the ADC channel and the DAC channel.
This refers to the data transfer. Since the device is synchronous, the
signal data words from the ADC channel and to the DAC channel occur
simultaneously.
This refers to the digital control data transfer into DIN and the register
read data from D
OUT
. The control mode interval occurs when
requested by hardware or software.
Frame sync refers only to the falling edge of the signal which initiates
the data transfer interval. The primary frame sync starts the Data Mode
and the secondary frame sync starts the Control Mode.
The time between falling edges of successive primary frame sync
signals.
This term refers to all signal processing circuits between the analog
input and the digital conversion result at D
OUT
.
This term refers to all signal processing circuits between the digital
data word applied to D
IN
and the differential output analog signal
available at OUT+ and OUT- pins.
This term refer to the ratio between the master clock MCLK
corresponding to the oversampling frequency and the sampling
frequency FS.
The number of bits in the input words to the DAC, and the output words
in the ADC.
The S/(N+D) with a 1kHz, -20dBr input signal and extrapolated to full
scale. Use of a small input signal reduces the harmonic distortion
components of the noise to insignificance. Units in dB or in N
bit
as
explained before.
S/(THD+N) is the ratio of the rms of the input signal to the rms of all
other spectral components within the measurement bandwidth
(0.425 x Sampling Frequency). Units in dB.
The amount of 1kHz signal present on the output of the grounded input
channel with 1kHz 0dB signal present on the other channel. Units
in dB.
PSRR. The amount of 1kHz signal present on the output of the
grounded input channel with 1kHz 200mV
PP
signal present on the
power supply.
Signal Data
Data Mode
Control Mode
Frame Sync.
Frame Sync and
Sampling Period
ADC Channel
DAC Channel
OverSampling Ratio
Resolution
Dynamic Range
Signal-to-(Noise+Distortion)
Crosstalk
Power Supply Rejection Ratio
STLC7550
15/17
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STLC8100 | DUAL BAND WIRELESS LAN RF TRANSCEIVER |
| STLIB4HDS | Development Environment For ST16 and ST19 Smartcard MCU Families |
| ST16-19HDSE | Development Environment For ST16 and ST19 Smartcard MCU Families |
| ST16-19 | Pulse Width Modulation (PWM) Controller IC; Topology:Buck (Step Down); Control Mode:Current, Voltage; Number of PWM Outputs:2; Input Voltage Primary Min:3V; Input Voltage Primary Max:6.5V; Oscillator Frequency Max, Fosc:2MHz |
| ST16-19RFRDCS | CHIP SET INTERFACE SPECIFICATION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STLC7550TQF7 | 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| STLC7550TQF7TR | 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| STLC7550TQFP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW POWER LOW VOLTAGE ANALOG FRONT END |
| STLC75C53TQFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM |
| STLC8100 | 制造商:STMicroelectronics 功能描述:RF TRNSCVR 5GHZ 48TQFP - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。