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參數資料
| 型號： | STLC7550 |
| 廠商： | 意法半導體 |
| 英文描述： | LOW POWER LOW VOLTAGE ANALOG FRONT END |
| 中文描述： | 低電壓低功耗模擬前端 |
| 文件頁數： | 10/17頁 |
| 文件大?。?/td> | 174K |
| 代理商： | STLC7550 |
6 - CONTROL REGISTER
This section defines the control and device status
information. The register programming occurs only
during Secondary Frame Synchronization. After a
reset condition, the device is always in data mode.
Table 3 :
Bits Assignment
Bits
Name
Function
Reset
Value
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
-
-
Aux/Main Input
Receive Gain
Oversampling bit 0
Oversampling bit 1
Oversampling bit 2
Attenuator transmit bit 0
Attenuator transmit bit1
M Divider
Q0 Divider
Q1 Divider
Q2 Divider
M Divider and Test mode bit 0
M Divider and Test mode bit 1
Test mode bit 2
Test mode bit 3
D1
D2
D3
D4
D5
D6
D7
M
Q0
Q1
Q2
T0
T1
10
11
12
13
14
15
TEST2
TEST3
Table 4 :
Aux/Main Input
D1
0
1
Function
Main Receive Input
Auxiliary Receive Input
Table 5 :
Receive Gain
D2
Function
DIFFERENTIAL INPUT
0
1
0dB gain (commun mode fixed)
+6dB gain (commun mode non-fixed)
SINGLE ENDED (one input used, other at V
CM
)
0
1
-6dB gain (see Note 1)
0dB gain
Note 1 :
Not recommended case. Performances could be reduced.
Table 6 :
Oversampling Ratio
D5
D4
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
D3
0
1
0
1
0
1
0
1
Function
160
192
Reserved
Reserved
Reserved
64
96
128
Table 7 :
Transmit Attenuation
D7
0
0
1
1
D6
0
1
0
1
Function
Infinite
Reserved
-6dB
0dB
Table 8 :
Q Divider Clock Generator
D11
0
0
0
0
1
1
1
1
D10
0
0
1
1
0
0
1
1
D9
0
1
0
1
0
1
0
1
Function
Q divider = 5
Q divider = 6
Q divider = 7
Q divider = 8
Q divider = 4.5
Q divider = 5.5
Q divider = 6.5
Q divider = 7.5
Table 9 :
M Divider Clock Generator
D13
0
0
0
1
1
1
D12
0
0
1
0
1
1
D8
0
1
X
X
0
1
Function
M divider = 3
M divider = 4
Reserved
Reserved
M divider = 1
M divider = 2
Table 10 :
Reserved Mode
D15
X
D14
X
Function
Reserved for test
This two bits must be set to 0 for normal operation.
FUNCTIONAL DESCRIPTION
(continued)
STLC7550
10/17
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