參數(shù)資料
型號(hào)： STLC7546
廠商： 意法半導(dǎo)體
英文描述： MODEM (V.34bis) Analog Front End(調(diào)制解調(diào)器模擬前端)
中文描述： 調(diào)制解調(diào)器（V.34bis）模擬前端（調(diào)制解調(diào)器模擬前端）
文件頁(yè)數(shù)： 7/16頁(yè)
文件大?。?/td> 131K
代理商： STLC7546
2.2 - Receive Low Pass Filter
Itisa decimationfilter.Thedecimationisperformed
by two decimation digital filters : one decimation
FIR filter and one decimationIIR filter.
ThepurposeoftheFIRfilteris to decimate32 times
thedigital signal comingfrom the ADC modulator.
The IIR is a cascade of 5 biquads. It provides the
low-pass filtering needed to remove the noise re-
maining above half the sampling frequency. The
outputof the IIR will be processedby the DSP.
3 - Clock Generator
Themasterclock,MCLKisprovidedbytheuser.The
ADC and DAC are oversampled at the MCLK fre-
quency.MCLKis equalto theshiftclock usedin the
serialinterface.TheMCLK frequencyshouldbe :
MCLK= Oversamplingratio x Samplingfrequency
The clock generatorprovides, via an internal PLL,
theclocksneededforthe computationin thedigital
section.The MCLKclockis usedbythePLLforthe
clockreference.
4 - Host Interface
The Host interface consist of the shift clock, the
frame synchronization signal, the ADC-channel
dataoutput, and the DAC-channeldata input.
The STLC7546 internallygeneratestheshift clock
and frame-sync signal for the serial communica-
tion.Thesesignalsarederivedfromthe inputmas-
terclock (MCLK).Two modesof serialtransfer are
available. The first is the software mode for 15-bit
Figure 1 :
DataMode
transmitdatatransferand16-bitreceivedatatrans-
fer,and thesecondis thehardwaremode for16-bit
data transfer. Both modes are selected by the
Hardware Control pins (HC0, HC1).
The data to the device, input/outputare MSB-first
in 2’scomplement format (seeTable 1).
Table 1 :
Mode Selection
HC1
0
HC0
0
Selected mode
Software mode Data/control through the
LSB of the 16-bit word. LSB = 0 for data
and LSB = 1 for control. At the end of the
Secondary Frame Synchronization the
device automaticallyreturnsto data mode.
Hardware mode for datatransferonly. The
16-bit data word is input to the DAC. The
16-bit data word output is the ADC
conversion result (operation equivalent to
the softwaremode with LSB= 0).
Hardware mode for device programming
and control register read. Operation
equivalent to the Software mode with
LSB = 1. 16-bit data is written to or read
from the device during Primary Frame
Synchronization. During the Secondary
Frame Synchronization, the 16-bit control
information is input to the device and the
16-bitdataword outputistheRegisterread
data.
0
1
1
X
When Control Mode is selected, the device will
internallygenerateanadditionalFrameSynchroni-
zation Pulse (Secondary Frame Synchronization
Pulse)atthe midpointof theoriginalFramePeriod.
TheOriginalFrameSynchronizationPulsewill also
be referredto as the Primary Frame Synchroniza-
tion Pulse.
FUNCTIONALDESCRIPTION
(continued)
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
-
D15 D14
-
-
-
-
FS
SCLK
TxDI
HC1, HC0
Sampling period
00 or 01
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
-
D15 D14
-
-
-
-
TxDO
7
STLC7546
7/16
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