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參數(shù)資料
| 型號(hào)： | STLC7546 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | MODEM (V.34bis) Analog Front End(調(diào)制解調(diào)器模擬前端) |
| 中文描述： | 調(diào)制解調(diào)器（V.34bis）模擬前端（調(diào)制解調(diào)器模擬前端） |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 131K |
| 代理商： | STLC7546 |
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4 - ANALOG INTERFACE
(9pins)
4.1 - DAC and ADC Positive Reference
Voltage Output
(V
REFP
)
This pin provides the Positive Reference Voltage
used by the 16-bit converters. The reference volt-
age, V
REF
, is the voltage difference between the
V
REFP
and V
REFN
outputs, andits nominal value is
2.5V. V
REFP
should be externally decoupled with
respectto V
CM
.
4.2 - DAC and ADC Negative Reference
Voltage Output
(V
REFN
)
This pin provides the Negative ReferenceVoltage
usedby the16-bitconverters,andshouldbe exter-
nally decoupledwith respectto V
CM
.
4.3 - Common Mode VoltageOutput
(V
CM
)
This output pin is the common mode voltage
(AV
DD
- AGND)/2. This output must be decoupled
withrespect to GND.
4.4 - Non-inverting Smoothing Filter
Output
(OUT+)
This pin is the non-inverting output of the fully
differentialanalog smoothing filter.
4.5 - InvertingSmoothing Filter Output
(OUT-)
Thispinistheinvertingoutputof thefullydifferential
analog smoothing filter. Outputs OUT+ and OUT-
provideanalogsignalswithmaximumpeakto peak
amplitude 2 x V
REF
, and must be followed by an
externaltwopolesmoothingfilter.Theexternalfilter
follows the internal single pole switch capacitor
filter.Thecutofffrequencyof theexternalfilter must
be greater than two times the sampling frequency
(FS), so that the combined frequencyresponse of
both the internal and external filters is flat in the
passband. The attenuatorof the lastoutput stage
can be programmedto 0dB,6dB or infinite.
4.6 - Non-invertingAnalog Input
(IN+)
This pin is the differentialnon-invertingADC input.
4.7 - InvertingAnalog Input
(IN-)
This pin is the differential inverting ADC input.
Theseanaloginputs(IN+, IN-)are presentedto the
Sigma-Deltamodulatorvia a multiplexer.The ana-
loginputpeaktopeakdifferentialsignalrangemust
be lessthan2 x V
REF
, andmustbeprecededby an
external single pole anti-aliasing filter. The cut-off
frequency of the filter must be lower than one half
the over-samplingfrequency(MCLK).Thesefilters
should be set as close as possible to the IN+ and
IN- pins. The gainof the first stageis 0dB and can
be programmed to 6dB in differential hardware
configuration.
4.8 - Non-inverting Auxiliary Analog
Input
(AUX IN+)
Thispinisthedifferentialnon-invertingauxiliaryADC
input.ThecharacteristicsaresameastheIN+input.
4.9 - InvertingAuxiliaryAnalog Input
(AUX IN-)
This pin is the differential inverting auxiliary ADC
input.ThecharacteristicsaresameastheIN-input.
The input pair (IN+/IN- or AUX IN+/AUX IN-) are
software selectable.
5 - TEST
(3 pins)
5.1 - TestOutputs
(TSTD1)
Digital output reserved for test. Can be left open.
5.2 - TestInput
(TSTD2)
Digitalinputreservedfortest.Shouldbe connected
to GND.
5.3 - AnalogTest Output
(TSTA)
Analog output reserved for test. Can be left open.
PIN DESCRIPTION
(continued)
STLC7546
5/16
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