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參數(shù)資料
| 型號(hào)： | STLC7546 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | MODEM (V.34bis) Analog Front End(調(diào)制解調(diào)器模擬前端) |
| 中文描述： | 調(diào)制解調(diào)器（V.34bis）模擬前端（調(diào)制解調(diào)器模擬前端） |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 131K |
| 代理商： | STLC7546 |
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1 - POWERSUPPLY
(5 pins)
1.1- AnalogV
DD
Supply
(AV
DD
)
Thispinisthepositiveanalogpowersupplyvoltage
(4.75Vto 5.25V)fortheDACand theADCsection.
It is not internally connected to digital V
DD
sup-
ply (DV
DD
).
In any case the voltageon this pin must be higher
or equal to the voltage of the Digital power sup-
ply (DV
DD
).
1.2 - DigitalV
DD
Supply
(DV
DD
)
This pin is the positivedigital power supply
for DAC and ADC digitalinternalcircuitry.
1.3- AnalogGround
(AGNDT,AGNDR)
Thesepinsarethegroundreturnof theanalogDAC
(ADC) section.
1.4 - DigitalGround
(DGND)
This pin is the ground for DAC and ADC internal
digital circuitry.
Notes :
1. To obtain published performance, the analog V
and
Digital V
should be decoupled with respect to Analog
GroundandDigitalGround,respectively.Thedecoupling
is intended to isolate digital noise from the analog
section ; decoupling capacitors should be as close as
possibleto therespective analog and digital supply pins.
2. Allthe groundpins mustbe tiedtogether.In the following
section, the ground and supply pins are referred to as
GND and V
DD
, respectively.
2 - HOST INTERFACE
(8pins)
2.1 - Data In
(D
IN
)
InData Mode,thedatawordis theinputof theDAC
channel.InControlMode,thedatawordis followed
by the control register word.
2.2 - Data Out
(D
OUT
)
InData Mode,thedatawordistheADCconversion
result. In Control Mode, the data word is followed
by the register read.
2.3 - Frame Synchronization
(FS)
Theframesynchronizationsignalisusedtoindicate
that the device is ready to send and receive data.
The data transferbegins on the falling edge of the
frame-sync signal. The frame-sync is generated
internallyandgoeslow onthe rising edgeof SCLK.
2.4 - SerialBit Clock
(SCLK)
Clocks the digital data into D
IN
and out of D
OUT
during the frame synchronizationinterval. The Se-
rialbit clockisgeneratedinternallyandequalto the
Master clocksignal frequency.
2.5 - ResetFunction (
RESET
)
The reset functionis to initializetheinternal count-
ers and control register. A minimum low pulse of
100ns is required to reset the chip. This reset
function initiates the serial data communications.
The reset functionwill initialize all the registersto
their default value and will put the device in a
pre-programmed state. After a low-going pulse on
RESET, the device registers will be initialized to
provide an over-sampling ratio equal to 160, the
serial interface will be in data mode, the DAC
attenuationwill be set to infinite, the ADC gain will
be set to 0dB, the Differential input mode on the
ADCconverterwillbe selected,andthemultiplexor
will be set on the main inputs IN+ and IN-. After a
resetcondition,thefirst framesynchronizationcor-
responds to the primarychannel.
2.6 - PowerDown (
PWRDWN
)
The Power-Down input powers down the entire
chip (<50
μ
W). When PWRDWN pin is taken low,
the device powers down such that the existing
internally programmed state is maintained. When
PWRDWN is driven high, full operation resumes
after 1ms.
If thePWRDWNinputis not used,it shouldbe tied
to V
DD
.
2.7 - HardwareControl
(HC0, HC1)
These two pins are used for Hardware/Software
Control of the device. The data on HC0 and HC1
will be latched on to the device on the rising edge
of the Frame Synchronization Pulse. If these two
pins are low, Software Control Mode is selected.
When in Software Control Mode, the LSB of the
16-bit word will select the Data Mode (LSB = 0) or
the ControlMode(LSB= 1).Othercombinationsof
HC0/HC1 are for Hardware Control. These inputs
shouldbe tied low if not used.
3 - CLOCK SIGNALS
(3 pins)
3.1 - MasterClock
(MCLK)
Masterclock input.Thissignal is the oversampling
clockof theD/AandA/D convertor.It alsoprovides
all theclocksof theserial interface.Thisinput may
be drivenby a CMOSsignal witha frequencyfrom
0.5MHzup to 2.88MHz(maximum).
3.2 - VoltageControl
(VC1, VC2)
The voltagecontrol output from the internal PLL.
If DV
DD
= 3.3V, VC2 should be tied to ground
throughacapacitorandVC1mustbetiedto ground
through a resistor.
If DV
DD
= 5V,VC1 andVC2 can be tiedto ground.
PIN DESCRIPTION
STLC7546
4/16
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