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參數(shù)資料
| 型號(hào)： | STLC7546 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | MODEM (V.34bis) Analog Front End(調(diào)制解調(diào)器模擬前端) |
| 中文描述： | 調(diào)制解調(diào)器（V.34bis）模擬前端（調(diào)制解調(diào)器模擬前端） |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 131K |
| 代理商： | STLC7546 |
DEFINITION AND TERMINOLOGY
Data Transfer Interval
The time during which data is transfered from D
OUT
and to D
IN
. This
intervalis 16 shiftclocks provides by the chip.
This refers to the input signal and all the converted representations
through the ADC channel and the DAC channel.
This refersto the data transfer. Since the device is synchronous,the
signaldatawordsfromtheADCchannelandto theDACchanneloccur
simultaneously.
This refersto thedigital controldata transferinto DIN andtheregister
read data from D
OUT
. The control mode interval occurs when
requestedby hardwareor software.
Frame syncrefers onlyto thefalling edge of thesignal which initiates
thedatatransferinterval.TheprimaryframesyncstartstheDataMode
and the secondaryframe sync starts the Control Mode.
The time between falling edges of successive primary frame sync
signals.
This term refers to all signal processingcircuits between the analog
input and the digital conversionresult at D
OUT
.
This term refers to all signal processing circuits between the digital
data word applied to D
IN
and the differential output analog signal
availableat OUT+ and OUT- pins.
This term refer to the ratio between the master clock MCLK
corresponding to the oversampling frequency and the sampling
frequency FS.
Thenumberof bitsintheinputwordsto theDAC,andtheoutputwords
in the ADC.
The S/(N+D) with a 1kHz, -20dBr inputsignal and extrapolatedto full
scale. Use of a small input signal reduces the harmonic distortion
components of the noise to insignificance. Units in dB or in N
bit
as
explained before.
S/(THD+N) is the ratio of the rms of the inputsignal to the rms of all
other spectral components within the measurement bandwidth
(0.425 x SamplingFrequency).Units in dB.
Theamountof1kHzsignalpresentontheoutputof thegroundedinput
channel with 1kHz 0dB signal present on the other channel. Units
in dB.
PSSR. The amount of 1kHz signal present on the output of the
grounded input channel with 1kHz 200mV
PP
signal present on the
power supply.
Signal Data
Data Mode
Control Mode
FrameSync.
FrameSync and
SamplingPeriod
ADCChannel
DACChannel
OverSamplingRatio
Resolution
DynamicRange
Signal-to-(Noise+Distortion)
Crosstalk
PowersupplyRejection Ratio
STLC7546
14/16
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| STLC7546CFN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM CIRCUIT|ANALOG FRONT END|CMOS|LDCC|28PIN|PLASTIC |
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