
FUNCTIONAL DESCRIPTION
(continued)
DGND - Ground Digital
ILIM - Current Limit Programming(Input)
ILIM programs the current limit of the Output driv-
ers using an external resistor connectedbetween
ILIM and VBB. The ILIM pin is 1.25V more posi-
tive than VBB. The current limit is 5mA plus 1000
times the current in the external resistor. The pro-
grammed current limit applies to each driver.
INT - Interrupt (Output; Open-Collector, Active
Low)
INT augments the Microprocessor Interface by
generating an interrupt when a Current Overload
Detector (COD) occurs. INT is active whenever
any bits in the COD register are active. INT is not
latched; when the COD register is zero, INT goes
inactive (High). INT will also go inactive if the
IQFPS automatically disables the S-output driver
that caused the interrupt (due to Thermal Over-
load), or if the microprocessor disables that line
via the Line Enable Register (LER). COD inter-
rupts can be masked via the Indirect Address
Register (IAR); RESET always disables the INT
pin.
RD - Read (Input;Active Low)
The active Low read signal is conditioned by CS
and transfers internal information to the data bus.
If A0 is a logical 0, logic levels of the Indirect Ad-
dress Register (IAR) and Thermal Shutdown
Status bit will be transferred to D3-D0. If A0 is a
logical 1, the data addressed by the IAR will be
transferredto D3-D0.
RESET- Reset (Input; Active High)
RESET initialize the registers in the device, leav-
ing the drivers switched off.
S3-S0 - Drivers(Output)
S3-S0 each supplypower to one line. The outputs
can sink up to 120 mA each. The voltage at the
line is connectedto VBB through a DMOS switch.
VBB - BatteryVoltage (input)
VBB is the internal negative supply voltage. VBB
must always be connected to the most negative
supply voltage. The MPI Registers will not func-
tion properly when the battery power is discon-
nected, that is, when VBB is floating or grounded.
The IQFPS should also be reset if a drastic tran-
sient is appliedto VBB.
VCC - +5VPower Supply (Input)
WR - Write (Input; Active Low)
The active Low write signal is conditioned by CS
and transfers information from the data bus to an
internal register selected by A0. If A0 is a logical
1, D3-D0 is written into the Line Enable Register
(LER). If A0 is a logical 0, D3-D0 is written into
the IAR. LER and IAR are the only two writable
registersin thedevice.
STLC5444
4/17