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參數(shù)資料
| 型號： | STLC5444 |
| 廠商： | 意法半導體 |
| 英文描述： | Quad Feed Power Supply(ISDN四饋電電源) |
| 中文描述： | 四飼料電源（綜合業(yè)務數(shù)字網(wǎng)四饋電電源） |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 140K |
| 代理商： | STLC5444 |
PIN DESCRIPTION
Name
N
o
PLCC
1
2,4,8,10,
13,14,
16,18,
20,23,
25,26,
28,34,
37,38,44
3
5
6,7
15,17
22,29,
39,40
9
11
12
19
21
24
–
27
30
31
32
33
35
36
41
42
43
N
o
DIP
1
7,9
Function
D1
NC
Bit 1of the tri state I/O data bus
No connection
D0
INT
VBB
2
3
Bit 0of the tri state I/O data bus
Active low interrupt output for the
μ
P (open drain)
Battery supply line (negative battery‘s terminal)
8,12
BGND
VCC
ILIM
S0
S1
S2
RSRVD
S3
RESET
RD
CS
WR
ALE
DGND
A0
D3
D2
4
5
6
Battery ground line
+5V supply line
Current limit programming
Output of the power switch controller 0
Output of the power switch controller 1
Output of the power switch controller 2
Reserved pin:it must be left floating
Output of the power switch controller 3
Active high reset input
Active low read input
Active low chip select input
Active low write input
Active high address latch enable
Digital ground
Address bit for R/W operations on the data bus
Bit 3of the I/O tristate data bus
Bit 2of the I/O tristate data bus
10
11
13
14
15
16
17
18
19
20
21
22
23
24
FUNCTIONAL DESCRIPTION
ADDRESS LINE (Input)
A0 selects source and destination locations for
read and write operations on the data bus. A0
must be valid on the falling edge of ALE or during
RD and WR if ALE is tied High.
ALE - Address Latch Enable (Input; Active
High)
ALE is an input control pulse used to strobe the
address on the A0 line into the address latch.
This signal is active High to admit the input ad-
dress. The address is latched on the High-Low
transition of ALE. While ALE is High, the address
latch is transparent. For an unmultiplexed micro-
processor bus, ALE must be tied High.
BGND - Ground Battery
CS - Chip Select(Input; Active Low)
CS must be Low to enable the read or write op-
erations of the device. Data transfer occurs over
the D3-D0 lines.
D3-D0 - DATA BUS (Input/Output; Three-State)
The four bidirectional data bus lines are to ex-
change information with a microprocessor. D0 is
the least significant bit and D3 is the most signifi-
cant bit. A High on the data bus corresponds to a
logical 1. These lines act as input when WR and
CS are active and as output when RD and CS are
active. When CS is inactive, the D3-D0 pins are
placed in a high-impedancestate.
STLC5444
3/17
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相關代理商/技術參數(shù) |
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| STLC5444B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:QUAD FEEDER POWER SUPPLY |
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| STLC5445 | 功能描述:監(jiān)控電路 Asics RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| STLC5460 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LINE CARD INTERFACE CONTROLLER |
| STLC5460FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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