
LER :
Bit
0
1
2
3
Logical 1
O0 on
O1 on
O2 on
O3 on
Logical 0 (default value)
O0 off
O1 off
O2 off
O3 off
The Line Enable Register (LER) is usedto enable or disable the individualoutput line drivers. The output
line will only become active if the correspondingbit in the TOR is set to a logical1. The LER can be writ-
ten directlyand read indirectly.
ABSOLUTE MAXIMUM RATINGS
(T
A
= 0
°
C to 70
°
C)
Parameter
Value
Voltage from Digital Input to DGND
Voltage from V
CC
to DGND
Voltage from V
BB
to DGND
100ns Pulse voltage from Si to DGND (See Notes)
Voltage from BGND to DGND
Storage Temperature
-0.4V to V
CC
-0.4V to +7V
-130V to +0.4V
-130V to +2V
+0.5V, -3V
T = -60
°
C to +150
°
C
Note
: Si stands for O0,O1, O2 or O3 outputs.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol1
T
A
T
A
V
CC
V
BB
DGND
BGND
I
SLIM
Min.
0
-40
4.75
-115
0
-3
Max.
70
85
5.25
-38
0
+0.5
120
Units
°
C
°
C
V
V
V
V
mA
(*) Ambient Temperature
for standard type
for ext. temperature type
Supply Voltage
Programmed Limiting Current
Note:
The test conditionis specified with a diode in series withV
.
(*)
: Specifications in this datasheet are guaranteed by testing from 0
°
C to +70
°
C. For extendedtemperature range types, performance from
–40
°
C to +85
°
C is guaranteed by characterization and periodic sampling of production units.
APPLICATION HINT
In the Absolute MaximumRatings table it is speci-
fied that the voltage applied on the -V
bat
pin
should never exceed by more than 0.4V the volt-
age appliedon the Groundpin.
As long as the external circuitry assures compli-
ance with the above, no more considerations are
needed.
In some cases however it may be not possible to
exclude that conditions may occur (hot insertion,
power supply transients, etc.) where the negative
supply has a transient overshoot above ground
voltage. Then a protection circuitry that clamps
such overshoot can add to the equipmentreliabil-
ity. Such protection can be designed taking into
considerations that typically the devices behave
as follows:
- if the V
bat
pin is not connected, and the other
pins are normally biased, the chip generates
on it an open circuit voltage of +420mV.
- if all the other pins are normally biased and
the -V
bat
pin forced at +600mV, a current of
10mA flows into it. At the same time from +5V
a current of 4mA is absorbed(this low current
from +5V simply means that no parasitic
latch-ups are triggered inside the chip). No
deteriorationof the device occurs.
- if all the other pins are normally biased, and
the -V
bat
pin is forced at +1.5V for a transient
period, no deterioration of the device occurs.
Transient period can be considered any time
interval that lasts for less than 10
μ
s andis not
repeated more than 5000 times during the
device lifetime.
ORDERINGTYPES:
STLC5444B1,PDIP24 package:0 to 70
°
CTemperature range.
STLC5444FN,PLCC44 package:0 to 70
°
C Temperaturerange.
STLC5444B1-X,PDIP24 package:-40 to 85
°
C Temperaturerange.
STLC5444FN-X,PLCC44 package:-40 to 85
°
CTemperature range.
STLC5444
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