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參數資料
| 型號： | STLC5412P |
| 廠商： | 意法半導體 |
| 英文描述： | 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE |
| 中文描述： | 2B1Q U接口裝置加強與無繩模式 |
| 文件頁數： | 8/74頁 |
| 文件大小： | 655K |
| 代理商： | STLC5412P |
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PIN FUNCTIONS
(specificGCI mode)
Pin
6
Name
FSa
In/Out
In Out
Description
Input or Output depending of the configuration. FSa is a 8 KHz clock which
indicates the start of the frame on Bx and Br.
In NT/TE non auto-mode configuration, FSb is a 8 KHz pulse always
indicating the second 64Kbit/sec channel of the frame on Br.
When MO = 0 (LT/NT12 configuration): S0 associated with S1 and S2
selects a GCI channel number on Bx/Br.
Input pin to select a transmission testin all auto mode configurations.
TEST2 is associated with TEST1.
2B+D and GCI control channel open drain output. Data is shifted out (at the
half BCLK frequency) on the first rising edge of BCLK duringthe assigned
channels slot. Br is in high impedance state outsidethe assigned time slot
and during the assigned time slot of a channel if it is disabled.
Bit clockinput or outputdepending of the configuration. When BCLK is an
input, its frequency may beany multipleof 16 KHz from 512 KHz to 6176
KHz.. When BCLK is an output, its frequency is 512KHz in NT1 auto and
NTRR auto configurations, 1536 KHz in NT/TE configuration; In this case,
BCLK is locked to the recovered clock received from the line. Input or
Output BCLK issynchronous with FSa. Data are shifted in and out (on Bx
and Br) at half the BCLK frequency.
2B+D and GCI control channel input. Data issampled by the UID on the
second falling edge of BCLK within the period of the bit, during the assigned
channels time slot.
General purpose programmable I/O configured by CR5 register in all non
auto mode configurations.
Input pin to select a transmission testin all auto mode configurations.
TEST1 is associated with TEST2.
General purpose programmable I/O configured by CR5 register in all non
auto mode configurations.
External control output pin inNT1 auto configuration. Normaly high, this pin
is pulled low when an eoc message ”operate 2B+D loopback” is recognized
from the line.
Local febe select:
When tied to 1 the febe is locallylooped back. See figure 10.
General purpose programmable I/O configured by CR5 register in all non
auto mode configurations.
External control output pin inLTRR auto configuration. Normaly high, this
pin is pulled low when an ARL command is received by the UID.
External status input pin. In NT1 auto and NTRR auto configurations, this
status is sent on the line through the ps2 bit.
When MO = 0 (LT/NT12 configuration): S2 associated with S0 and S1
selects a GCI channel number on Bx/Br.
When MO = 1: Configuration input pin. Is usedassociated with CONF1 to
select configuration NT/TE (non auto), NT1 auto, LTRR auto and NTRR
auto.
General purpose programmable I/O configured by CR5 register in all non
auto mode configurations.
External status input pin. In NT1 auto and NTRR auto configurations, this
status is sent on the line through the ps1 bit.
PLL1 can be disabled in LTRR configuration with this pin.
When MO = 0 (LT/NT12 configuration): S1 associated with S0 and S2
selects a GCI channel number on Bx/Br.
When MO = 1: Configuration input pin. Is usedassociated with CONF2 to
select configuration NT/TE (non auto), NT1 auto, LTRR auto and NTRR
auto.
7
FSb
Out
S0
In
TEST2
In
11
Br
Out
12
BCLK
In Out
13
Bx
In
14
IO4
In Out
TEST1
In
15
IO3
In Out
EC
Out
LFS
In
16
IO2
In, Out
EC
Out
ES2
In
17
S2
In
CONF2
In
18
IO1
In Out
ES1
In
PLLD
S1
In
In
19
CONF1
In
STLC5412
8/74
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