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參數(shù)資料
| 型號(hào)： | STLC5412P |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE |
| 中文描述： | 2B1Q U接口裝置加強(qiáng)與無繩模式 |
| 文件頁數(shù)： | 7/74頁 |
| 文件大小： | 655K |
| 代理商： | STLC5412P |
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PIN FUNCTIONS
(specificMicro Wire mode)
Pin
12
Name
BCLK
In/Out
In Out
Description
Bitclockinputor output depending oftheCMSbit inCMRregister. WhenBCLK is
aninput, itsfrequency maybeanymultipleof8 KHzfrom256KHzto4096 KHz in
formats1,2,3;512KHz to6176KHzinformat4.WhenBCLK isanoutput,its
frequency is 256KHz,512KHz,1536 KHz,2048KHzor2560KHzdepending of
theselection inCR1 register.Inthis case,BCLK is lockedto therecoveredclock
receivedfromtheline. InputorOutputBCLKissynchronous withFSa/FSb.Datas
areshiftedinandout (onBxandBr) attheBCLK frequency informats1,2,3.In
format4 datasareshiftedoutathalf theBCLKfrequency.
2B+D input. Basic access data to transmit to the line is shiftedin on the
falling edges (at the BCLK frequency or the half BCLK frequency if format 4
is selected) during the assigned time-slots. WhenD channel port is
enabled, only B1 & B2 sampled on Bx.
D channel clock output when the D channel port is enabled in continuous
mode. Datas are shifted in and out (on Dx and Dr) at 16 KHz on the falling
and rising edges of DCLK respectively. In master mode, DCLK is
synchronous with BCLK.
D channeldata output when the D channel port is enabled. D channel datais
shiftedout fromthe UID on this pin in 2 selectablemodes: inTDM mode data
isshiftedout at the BCLKfrequency (or half BCLK frequency in format 4) on
the ridsing edgeswhen the assigned time slot is active. Incontinuous mode
datais shifted in at the DCLKfrequency on the rising edge continuously.
D channel data input when the D channel port is enabled. D channel data is
shifted in from the UID on this pin in 2 selectable modes: in TDM mode data
is shifted in at the BCLK frequency (or half BCLK frequency in format 4) on
the falling edges when the assigned time slot is active. In continuous mode
data is shifted in at the DCLK frequency on the falling edge continuously.
Clock input forthe MICROWIREcontrolchannel: data isshifted inand out on CI
andCO pins withCCLKfrequency following 2 modes.Foreachmode theCCLK
polarity isindifferent. CCLKmay beasynchronous with allthe others UIDclocks.
MICROWIREcontrolchannel serial input:TwobytesdataisshiftedintheUID on
thispinontherisingorthefallingedgeofCCLK depending oftheworking mode.
MICROWIRE control channel serial output: two bytes data is shifted out the
UID on this pin on the rising or the falling edge of CCLK depending of the
working mode.When not enabled by CS low, CO is high impedance.
TxSuper framesynchronization. The rising edge ofSFSx indicates the
beginning of the transmit superframeon the line. In NT mode SFSxisalways
an output.In LT mode SFSx is aninput or an outputdepending of theSFS bit
in CR2register. WhenSFSx is input, it must besynchronous of FSa. InDECT
mode thispin is always an input in LT configuration and is used to evaluate the
round tripdelay, in NT configuration is an output used to resynchronise the
DECT framecounter.( refer to page25)
Rx Super frame synchronization. The rising edge of SFSr indicates the
beginning of the received superframe on the line. UID provides this output
only when ESFR bit in CR4 register is set to1.
Line Signal Detect output (default configuration): This pin is an open drain
output which is normally in the high impedance state but pulls low when the
device previously in the power down state receives a wake-up by Tone from
the line. This signal is intended to be usedto wake-up a micro-controller
from a low power idle mode. The LSD output goes back in the high
impedance state when the device is powered up.
Interruptoutput: Latched open-drain output signal which isnormally high
impedance and goes lowto request aread cycle.Pending interrupt data is
shiftedout fromCOat thefollowing read-write cycle.Severalpending interrupts
maybe queued internally and mayprovide several interrupt requests. INT is
freedupon receiving ofCS lowandcangolow again whenCS isfreed.
Chip Select input: Whenthis pin ispulled low, data can be shifted in and out
from the UID through CI & CO pins. When high, this pin inhibits the
MICROWIRE interface. For normal read or write operation, CS has to be
pulled low for 16CCLK periods.
13
Bx
In
14
DCLK
Out
15
Dr
Out
16
Dx
In
17
CCLK
In
18
CI
In
19
CO
Out
22
SFSx
In Out
25
SFSr
Out
LSD
Out
26
INT
Out
27
CS
In
STLC5412
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