參數(shù)資料
型號： STLC5412P
廠商： 意法半導體
英文描述： 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
中文描述： 2B1Q U接口裝置加強與無繩模式
文件頁數(shù)： 54/74頁
文件大?。?/td> 655K
代理商： STLC5412P
Table 9:
READBACK MESSAGES
FUNCTION
BYTE 1
AD3/1
000
001
010
011
100
101
110
111
000
001
010
011
100
101
000
001
010
011
100
101
110
EFG
CCC
EFG
000
BYTE 2
AD7/4
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
0011
0011
0100
0100
0100
0100
0100
0100
0100
0110
1000
1011
1100
AD0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
H
C
H
1
7
6
5
4
3
2
1
0
OPR
CR1
CR2
CR3
CR4
CR5
CR6
CR7
TXB1
TXB2
RXB1
RXB2
TXD
RXD
TXM4
TXM56
TXACT
BEC1
BEC2
ECT1
ECT2
TXEOC
IDR
DECTEOC
DBAUD
CIE
FF1
SFS
LB1
EB1
I04
T1SE
0
0
0
0
0
DX5
DR5
0
0
0
c7
c7
ECT17
ECT27
XEOC1
0
DEOC1
DBAUD7
EIE
FF0
NTS
LB2
EB2
I03
ACTUAT
0
0
0
0
0
DX4
DR4
M42x
0
0
c6
c6
ECT16
ECT26
XEOC2
0
DEOC2 DEOC3
DBAUD6
DBAUD5
DBAUD4
FIE
CK2
DMO
LBD
ED
I02
PUPAUT
0
B1X5
B2X5
B1R5
B2R5
DX3
DR3
M43x
0
0
c5
c5
ECT15
ECT25
XEOC3
0
OB1
CK1
DEN
DB1
FFIT
I01
QM
0
B1X4
B2X4
B1R4
B2R4
DX2
DR2
M44x
M51x
0
c4
c4
ECT14
ECT24
XEOC4
0
DEOC4
OB0
CK0
ETC
DB2
ESFr
D4
AIS
0
B1X3
B2X3
B1R3
B2R3
DX1
DR1
M45x
M61x
C4x
c3
c3
ECT13
ECT23
XEOC5
1
DEOC5
DBAUD3
0C1
DDM
BP1
DBD
CTLIO
D3
TFB0
LOCK
B1X2
B2X2
B1R2
B2R2
DX0
DR0
M46x
M52x
C3x
c2
c2
ECT12
ECT22
XEOC6
0
DEOC6 DEOC7
DBAUD2
0C0
CMS
BP2
TLB
MOB
D2
RFS
PL2EN
B1X1
B2X1
B1R1
B2R1
SX1
SR1
0
FEBx
C2x
c1
c1
ECT11
ECT21
XEOC7
0
C2E
BEX
RR
T15D
CTC
D1
LFS
DECT
B1X0
B2X0
B1R0
B2R0
SX0
SR0
M48x
FEBx
C1x
c0
c0
ECT10
ECT20
XEOC8
0
DEOC8
DBAUD0
DBAUD1
DTXRX
1100
001
1
DTXRX7
DTXRX6
DTXRX5
DTXRX4
DTXRX3
DTXRX2
DTXRX1
DTXRX0
Notes:
1. For allthese registers withtheexception ofTXEOC,bit 0 ofBYTE1 issetto 1to indicateread-backmessage.
2. CR5 configuration/status register is listed with status registers.
3. Bit 7 of BYTE 1 is the firstclocked out from the UID.
4. M42x is significantin NT mode only
Table 10:
SPONTANEOUSOR DRIVEN MESSAGES
FUNCTION
BYTE 1
AD3/1
101
111
000
001
010
011
100
EFG
BYTE 2
AD7/4
0010
0011
0100
0100
0100
0100
0100
0101
AD0
0
0
0
0
0
0
0
H
7
6
5
4
3
2
1
0
CR5
STATUS
RXM4
RXM56
RXACT
BEC1
BEC2
RXEOC
IO4
PWDN
M41R
0
0
c7
c7
REOC1
IO3
0
M42R
0
0
c6
c6
REOC2
IO2
0
M43R
0
0
c5
c5
REOC3
IO1
0
M44R
M51R
0
c4
c4
REOC4
D4
D3
D2
D1
RxFFU
M45R
M61R
C4R
c3
c3
REOC5
RxFFO
M46R
M52R
C3R
c2
c2
REOC6
TxFFU
M47R
FEBR
C2R
c1
c1
REOC7
TxFFO
M48R
NEBR
C1R
c0
c0
REOC8
Notes:
1. All status registers can be read by settingfirst the appropriate command. At any status change, an interrupt cycle is issued.
2. In theRXEOCregister:
E = ea1
F = ea2
G= ea3
H= d=0/m= 1
3. For all These registers with the exception ofRXEOC, bit 0 of BYTE 1 is set to 0 to indicate a status register.
STLC5412
54/74
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