參數(shù)資料
型號(hào)： STLC5412P
廠商： 意法半導(dǎo)體
英文描述： 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
中文描述： 2B1Q U接口裝置加強(qiáng)與無(wú)繩模式
文件頁(yè)數(shù)： 50/74頁(yè)
文件大小： 655K
代理商： STLC5412P
When Block error counter reachs this value, an
Interrupt relative to BEC2 register is loaded in the
interrupt stack. This can be used as an early
alarm in case of degradedtransmission.
Receive status Register - read command
(RXOH)
(Write only)
EOC
Reset to zero of all the RXOH bits is automatic.
EOC
ReceiveEOC status registerread.
When EOC bit is set to one, UID automatically
loads the current value of RXEOC register in the
interrupt stack independently of
change.
M4
M56
ACT
0
STATUS
0
RST
any
status
M4
Receive M4 overhead bits status register
read.
When M4 bit is set to one, UID automatically
loads the current value of RXM4 register in the in-
terrupt stackindependentlyof any statuschange.
M56
Receive M5 and M6 overhead bits status
registerread.
When M56 bit is set to one, UID automatically
loads the current value of RXM56 register in the
interrupt stack independently of
change.
any
status
ACT
Activationindication status.
When ACT bit is set to one, UID automatically
loads the current value of RXACT register in the
interrupt stack independently of
change.
In GCI mode, the RXACT read back always uses
the monitor channel.
any
status
STATUS
When STATUS bit is set to one, UID automat-
ically loads the current value of STATUS register
in the interrupt stack independently of any status
change.
RST
only).
When RST bit is set to one, UID is fully reset in-
cluding configurationregisters, state machine and
all coefficients and reset to their default value.
UID entersin the power-downstate.
RESET
(MICROWIRE/DSI
configuration
TransmitEOC register (TXEOC)
After reset:FFFH
XEOC1
XEOC2
XEOC3
XEOC4
XEOC5
XEOC6
XEOC7
XEOC8
TXEOC Register is constituted of 12 bits, 3 bits
address (EFG), 1 bit data/message Flag (H), 8
bits information (XEOC1 - XEOC8). When trans-
mitting SL2/SL3 or SN3 signal. STLC5412 shall
continuously send into the EOC channel field the
eoc bits twice per superframe. TXEOC register is
loaded in the transmit register at each half a su-
perframe.
The address of thisregister is composedonly of 4
bits. Read-back can be performed by means of a
read-backcommand 6100H.
Dect Mode Eoc Register(DECTEOC)
After reset: FFFH
DEOC1
12 bits register to store the DECT EOC message,
3 bits address (EFG), 1 bit data/message Flag
(H), 8 bits information (DEOC1 - DEOC8) This
register is significant only in DECT mode. In LT
DECT mode the byte is transmitted 3 times in the
EOC channel starting from the superframe identi-
fied by the DECSYNC pulse on the SFSx pin.
Once the DECTEOC byte has been transmitted 3
times, the content of the EOC channel returns to
the previous existing value. In NT DECT mode if
the received EOC message field is detected 3
times identical to the DECTEOC register, the de-
vice generates a pulse on the pin SFSx synchro-
nous with the SFSr pulse. Read back can be per-
formed by means of command B100H.
DEOC2
DEOC3
DEOC4
DEOC5
DEOC6
DEOC7
DEOC8
Receive EOC register(RXEOC)
(readonly)
After reset: FFFH
REOC1
The RX EOC Register is constituted of 12 bits.
When the line is fully activated (super frame syn-
chronized) and when a new eoc message is re-
ceived and validated in accordance with the crite-
ria selected in the Configuration Register OPR,
the RX EOC Register is queued in the interrupt
registerstack. The addressof this registeris com-
posedonly of 4 bits.
It is always possible to read this register by writ-
ing EOC = 1 in RXOH register
REOC2
REOC3
REOC4
REOC5
REOC6
REOC7
REOC8
IdentificationRegister (IDR)
Fixed value: CCCC 00001000
(readonly 12 bit register)
When a read-backoperation of IDR register is en-
tered, UID loads the Identification Register in the
interrupt stack. This register provides a reserved
identificationcode agreed by GCI standard:
CCCC 00001000
IDR registeris accessiblevia two addresses (See
page 34).
STLC5412
50/74
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