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參數(shù)資料
| 型號(hào)： | STLC5412P |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE |
| 中文描述： | 2B1Q U接口裝置加強(qiáng)與無繩模式 |
| 文件頁數(shù)： | 42/74頁 |
| 文件大小： | 655K |
| 代理商： | STLC5412P |
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area 00/0FH: NOPoperations.
area 10/1FH: test registers:reserved.
area 20/2FH: the configurationregisters.
OPRCR1 CR2 CR3 CR4 CR5
CR6 CR7
Read Write access. CR5 only
usefullin GCI mode
area 30/3FH: the B1 B2 D time slot registers.
TXB1 TXB2 RXB1 RXB2 TXD
RXD STATUS
Read Write access except
STATUS:Read only.
Usefullonly in
μ
W mode
except STATUS:
μ
W & GCI
modes.
area 40/4FH: the transmit and receive
registers(except EOC).
TXM4RXM4 TXM56RXM56
TXACT RXACTBEC1 BEC2
ECT1ECT2 RXOH
Read Write access for the
transmit registers:
TXM4TXM56TXACT
Read access only for the
receive registers:
RXM4RXM56 RXACT
Read Write access for the
control registers:
ECT1 ECT2
Read access only for the error
registers:
BEC1 BEC2
Writeaccess only for the
command registers:
RXOH
area5xtoBx:
5x:
to writeTXEOC register,to read
RXEOC register.
to read TXEOCregister.
reserved
to read IDR register.
to writeDECTEOC register
to read DECTEOC register
to read round trip delay registers
reserved
reserved except FF address:
special registerMWPS.
6x:
7x:
8x & 9x:
Ax:
Bx:
areaC0/C3H:
areaC4HtoEx:
area Fx:
for 12 bits registers.
Overhead bitsProgrammableRegister (OPR)
After reset:1EH
CIE
CIE
Near-EndCRC Interrupt Enable:
EIE
FIE
OB1
OB0
OC1
OC0
C2E
CIE = 1: the RXM56 register is queuedin the
interrupt register stackwith nebe bit
set to zero each time the CRC result
is not identical to the corresponding
CRC received from the line.
CIE = 0: no interruptis issued but the error
detectionremains active for instance
for on chip error counting.
EIE
Error countingInterrupt Enable:
EIE = 1: an interruptis providedfor the
counter when the threshold(ECT1 or
ECT2) is reached.
EIE=0:
no interruptis issued.It is feasible to
read the counters even if no relevant
interrupt has been provided.
FIE
FEBElnterrupt Enable:
FIE= 1:
the RXM56registeris queuedinto
the interruptregister stack each time
the febe bit is receivedat zeroin a
superframe.
no interruptis issued but thereceive
febebit remainsactive for on chip
error counting.
FIE= 0:
OB1,OB0
OverheadBit processing:
select how each spare overheadbit received from
the line is validated and transmitted to the sys-
tem. RXM4 and RXM56 registers are inde-
pendently provided onto the system interface as
for the eoc channel. Each spare overhead bit is
validated independentlyfrom the others.
OB1
0
OB0
0
each super frame, an interrupt
is generated for the RXM4 or
the RXM56 register. Spare bits
are transparently transmited to
thesystem.
an interrupt is set at each new
spare overhead bit(s) received.
an interrupt is set at each new
spare overhead bit(s) received
and confirmed once. ( two
times identical).
an interrupt is set at each new
spare overhead bit(s) received
and confirmed twice. (three
times identical).
0
1
1
0
1
1
If new bits are received at the same time in M4
STLC5412
42/74
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