參數(shù)資料
型號： STLC5412P
廠商： 意法半導(dǎo)體
英文描述： 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
中文描述： 2B1Q U接口裝置加強與無繩模式
文件頁數(shù)： 25/74頁
文件大小： 655K
代理商： STLC5412P
with arbitraryphase.
ELASTICBUFFERS
The UID buffers the 2B+D data in elastic fifos
which are 3 line-frames deep in each direction.
When the Digital Interfaceis a timing slave, these
FIFOs compensate for relative jitter and wander
between the Digital Interface and the line. Each
buffer can absorb wander up to 18
μ
s at 80 KHz
max without ”slip”. This is particulary convenient
for NT1-2 or PABX application in case the local
reference clock is jitterized and wandered relative
to the incoming signal from the line.
DECT SYNCHRONIZATION
In a DECT system the U interface is used for digi-
tal transmission between the base station control-
ler (LT) and the base station (NT). The U inter-
face allows the transmission of 4 DECT channels
through B1, B2 using ADPCM compression. Be-
side the D channel allows the exchangeof signal-
ling information between the base station control-
ler (BSC)and the base station(BS).
Seamless handover (for switching the radio-com-
munication from one base station to another) re-
quires additional features in U interface circuit for
base stationssynchronisation.
DECT OrientedFeatures In U Interface
Possibility to measure the round-trip delay be-
tweenBSC and BS.
The different delay of each BSC-BS connec-
tion can be compensated in each BS with a
preset counter that is loaded with the delay
value provided by the STLC5412 in the BSC
and sent to the BS via the D channel.
Round trip delay (RTD) measurement allows to
estimate the link delay (SFSrNT-SFSxLT =
RTD/2+Konst) with a total accuracy of +/- 200
nsec when STLC5412 is usedboth in BSC and
BS. The total accuracy is the sum of two con-
tributions. The process spread on internal
propagation delays (
±
166.5ns) and jitter on re-
covered clock in LT (
±
32.5ns).
DECT framessynchronisation.
The BSC must synchronise all the BSs con-
nected to itself. A synchronisation pulse DEC-
SYNC is provided by the network to all the
STLC5412 devices in the BSC (LT). The
STLC5412 devices synchronise the 2B1Q
frames on the U link with DECSYNC and send
an EOC message to the corresponding BS
(NT). The STLC5412 in the BS (NT) on recep-
tion of the EOC message provides a pulse to
preset the counter for DECT frame generation.
The jitter related to this pulse is the jitter of the
recovered clock in NT. Maximum jitter guaran-
teedon all ETSI loops is
±
130ns.
These two features allow the BSC to generate
synchronous DECT frames (160ms) and multi-
frames with maximum phase difference of
±
330ns.
LT DECT MODE
In LT DECT mode the STLC5412 provides round
trip delay estimation with a resolution of +/- 33
nsec. and automatic EOC DECT message trans-
fer for base stations synchronisation.
The DECSYNC pulse is applied to pin SFSx
(CR2.7=0). The DECSYNC period must be multi-
ple of 12ms and in phase with FSa. The SFSx in-
put pulse resets the line frame counter when the
device is in power-up. After power-up, before ac-
tivation, it is suggested to wait for the first avail-
able DECSYNC pulse. If not, the DECSYNC
pulse will generatea jump in the line synchronisa-
tion, that can cause a line deactivation.
Round trip delay estimation procedure
The round trip delay is the delay between
Transmit sync word (ISW) and receive Sync
word on the line. It can be estimated from
three parameters that can be read in internal
registers:
tdd:total digital delay
delay between SFSx and SFSr in steps of 12.5
μ
sec.It is availablein registerDBAUD0-4
edd: elastic digital delay
value to add to tdd that takes into account the
internal elastic memory state. It is available in
registerDBAUD5-7
ced: clock elastic delay
It providesthe phasedifference between trans-
mit and receive clocks in steps of 65.1 nsec.It
is available in register DTXRX. See Application
Note for use.
DECT EOC message transfer
If CR7.0 = 1 (DECT mode) a synchronisation
pulse on pin SFSx triggers the DECT EOC
message transfer. The message stored in
DECTEOC register is transmitted 3 times in
the EOC channel starting from the 1st avail-
able superframefollowing the DECSYNCpulse
on the SFSxpin. See ApplicationNote for use.
NT DECT MODE
In NT DECT mode the STLC5412 after recogni-
tion of DECT EOC messagestored in DECT EOC
register, generates a pulse on pin SFSx, synchro-
nous with next SFSr edge. In this way the
STLC5412 provides on pin SFSx a pulse used to
resynchronise the DECT frame counter in the
base station.
TheLOCK bit inCR7 registercan be usedto enable
thelockingofFSawithSFSr afterlineisactivated.
In particular the FSa rising edge will occur 62.5us
after the SFSr rising edge.
STLC5412
25/74
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