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參數(shù)資料
| 型號： | STLC5412P |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE |
| 中文描述： | 2B1Q U接口裝置加強與無繩模式 |
| 文件頁數(shù)： | 14/74頁 |
| 文件大小： | 655K |
| 代理商： | STLC5412P |
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FUNCTIONAL DESCRIPTION
Digital Interfaces
STLC5412 provides a choice between two types
of digital interface for both control data and (2
B+D) basic access data.
These are:
a) GeneralCircuit Interface:GCI.
b) Microwire/Digital System Interface:
μ
W/DSI
The device will automatically switch to one of
them by sensing the MW input pin at the Power
up.
μ
W/DSI MODE
Microwirecontrol interface
The MICROWIRE interface is enabled when pin
MW equal one. Internalregisters can be writtenor
read through thatcontrol interface.
It is constitutedof 5 pins:
CI:
CO:
CCLK:
CS:
INT:
data input
data output
data clockinput
Chip Select input
Interruptoutput
Transmission of data onto CI & CO is enabled
when CS input is low.
A Write cycle or a Read cycle is always consti-
tuted of two bytes. CCLK must be pulsed 16
times while CS is low.
Transmission of data onto CI & CO is enabled fol-
lowing 2 modes.
– MODE A: the first CCLK edge after CS fall-
ing edge (and fifteen others odd CCLK
edges) are used to shift in the CI data, the
even edges being used to shift out the CO
data.
– MODE B: the CCLK first edge after CS falling
edge (and the fifteen others odd CCLK
edges) are used to shift out the CO data, the
even edges being used to shiftin theCI data.
For each mode the first CCLK edge after CS fall-
ing edge can be positive or negative: the UID
automaticalydetectsthe CCLK polarity.
Mode A is the default value. To select the mode
B, writeMWPS register.
You can writein the UID on CI whilethe UID send
back a register content to the microprocessor. If
the UID has no message to send, it forces the CO
output to all zero’s.
If the UID is to be read (status change has oc-
cured in the UID or a read-back cycle has been
requested by the controller), it pulls the INT out-
put low until CS is provided. INT high to low
transition is not allowed when CS is low (the UID
waits for CS high if a pending interrupt occurs
while CS is low).
When CS is high,the CO pin is in the high imped-
ance state.
Writecycle
The format to write a 8 bits message into the UID
is:
A7
A6
A5
A4
1stbyte
A3
A2
A1
A0
D7
D6
D5
D4
2nd byte
D3
D2
D1
D0
A7-A1:
A0:
D7-D0:
RegisterAddress
Write/Read back Indicator
RegisterContent
After the first byte is shifted in, Register address
is decoded.A0 set low indicatesa writecycle: the
content of the following received byte has to be
loaded into the addressed register.
A0 set high indicates a read-back cycle request
and the byte following is not significant. The UID
will respond to the request with an interrupt cycle.
It is then possible for the microprocessor to re-
ceive the required register content after several
other pendinginterrupts.
To write a 12bitsmessage,the differenceis:
limited address field:
extendeddata field (D11 - D8): A3 - A0.
The Write/Read back indicator doesn’t apply; to
read and write a 12 bits register two addresses
are necessary.
A7 - A4
Read cycle
When UID has a register content to send to the
microprocessor, it pulls low the INT output to re-
quest CS and CCLKsignals. Note that the data to
send can be the content of a Register previously
requested by the microprocessor by means of a
read-backrequest.
The format of the 8 bits message sent by the UID
is:
A7
A6
A5
A4
1stbyte
A3
A2
A1
A0
D7
D6
D5
D4
2nd byte
D3
D2
D1
D0
A7-A1:
A0:
D7-D0:
RegisterAddress
forced to 1 if read back
forced to 0 if spontaneous
RegisterContent
STLC5412
14/74
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