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參數資料
| 型號： | STLC5412FN |
| 廠商： | 意法半導體 |
| 英文描述： | 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE |
| 中文描述： | 2B1Q U接口裝置加強與無繩模式 |
| 文件頁數： | 6/74頁 |
| 文件大?。?/td> | 655K |
| 代理商： | STLC5412FN |
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PIN FUNCTIONS
(no Specific Microwire / GCI Mode)
Note: all pin number are referred to PlasticDIP28 package.
Pin
1, 4
Name
LO+, LO-
In/Out
Out, Out
Description
Transmit 2B1Q signal differential outputs tothe line transformer. When
used with an appropriate 1:1.5 step-up transformer and the proper line
interface circuit the line signal conforms to the output specifications in ANSI
standard with a nominal pulse amplitudeof 2.5 Volts.
Receive 2B1Q signal differential inputs from the line transformer.
Positive power supply input for the analog and digital sections, which must
be +5 Volts +/-5% and must be directlyconnected together.
Negative power supply pins, which must be connected together close to
the device.
All digital and analog signals are referred to these pins,which are normally
at the system Ground.
(LT configuration only)
This pin is an open drain output normally in the high impedance state which
pulls low when B1 and B2 time-slots are active. It can be used to enable the
Tristate control of abackplane line-driver.
(NT configuration only)
15.36 MHz clock output which is frequency locked to the receivedline
signal active as soon as UID ispowered up exceptin NT1 Auto
configuration (active only if S line activation is requested)
The output of the crystal oscillator, which should be connected to one end
of the crystal, if used. Otherwise, this pin must be left not connected.
The master clock input, which requires either a parallel resonance crystal to
be tiedbetween this pin and XTAL2, or a logic level clockinput from a
stable source. This clock does not need to be synchronized to the digital
interface clocks (FSa, BCLK).Crystal specifications: 15.36 MHz +/-50ppm
parallel resonant; Rs
≤
20 ohms; load with 33pF to GND eachside.
MICROWIRE selection: When set high, MICROWIREcontrol interface is
selected. When set low, GCI interface is selected.
2, 3
5, 8
LI+, LI-
VCCA, VCCD
In, In
In, In
24, 9
23
GNDA,GNDD1
GNDD2
In, In
In
10
TSR
Out
SCLK
Out
20
XTAL2
Out
21
XTAL1
In
28
MW
In
PIN FUNCTIONS
(specificMicro Wire mode)
Pin
6
Name
FSa
In/Out
In Out
Description
Input or Output depending of the CMS bit in CR1 register, FSa is a 8 KHz
clock which indicates the start of the frame on Bx when FSa is input, orBx
and Br when FSa is output.
Input or Output, the location of FSa relative to the frame on Bx or Bx and Br
depends of DDM bit in CR1 register,also the selected format.
Input or Output depending of the CMS bit in CR1 register, FSb is a 8 KHz
clock which indicates the start of the frame on Br when it is an input. When
it is an output, FSb isa 8 KHz pulse conforming with the selected format
and always indicating the second 64Kbit/sec channel of the frame on Br.
Input or Output, the location of FSb relative to the frame on Br depends of
DDM bit in CR1 register, also the selected format.
2B+D datas tristate output. Datas received from the line are shifted out on
the rising edge (at the BCLK frequency or the half BCLK frequency if format
4 is selected) during the assignedtime slot. Br is in high impedance state
outside the assigned time slot and during the assigned time slot of the
channel if it is disabled.
When D channel port is enabled, only B1 B2 are on Br.
7
FSb
In Out
11
Br
Out
STLC5412
6/74
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