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參數(shù)資料
| 型號(hào)： | STLC5412FN |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE |
| 中文描述： | 2B1Q U接口裝置加強(qiáng)與無繩模式 |
| 文件頁數(shù)： | 55/74頁 |
| 文件大?。?/td> | 655K |
| 代理商： | STLC5412FN |
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LineInterface Circuit
It is very important, comply with ANSI, ETSI and
French standards, that the recommended line in-
terface circuit should be strictly adhered to. The
channel response and dynamic range of this cir-
cuit have been carefully designed as an integral
part of the overall signal processing system
to ensure that the performance require-
ments are met under all the specified loop
conditions. Deviations from this design are
likely to result in sub-optimal performance
or even total failure of the system on some
types of loops.
TurnsRatio: Np:Ns = 1:1.5.
SecondaryInductance:Lp 27mH.
Max leakageinductance:100
μ
H
Winding Resistances: 30 ohms
> 10 ohms.
Return Loss,at 40 kHz and load of 135 ohms: 26
dB. Saturationcharacteristics: THD –70dB when
tested with 50mA d.c. through the secondary and
a 40kHz sine-wave injected into the primary at a
level which generates, at the secondary, 5V
P-P
(R
load
= 135ohms).
List of suppliers:
SHOTT
PULSE ENGINEERING
(2.25Rp + Rs)
Table 11.
WINDING
NUMBER OF
TURNS
98 Single
120+120 Bifilar
62 Single
WIRE GAUGE
1-2
#34 AWG
#36 AWG
#34 AWG
6-5, 8-7
3-4
WINDING
1-2 + 3-4
5-6 + 7-8
INDUCTANCE
12 mH
27 mH
RESISTANCE
less than 5
less than 10
Board Layout
While the pins of the UID are well protectedagainst
electricalmisuse,it isrecommendedthatthe stand-
ard CMOS practise, of applying GND to the device
before any other connectionsare made, should al-
ways be followed. In applicationswhere the printed
circuit card may be plugged into a hot socket with
power and clocks already present, an extra long
groundpin on the connectorshouldbe used.Great
care must be taken in the layout of the printed cir-
cuit board in order to preserve the high transmis-
sion performance of the STLC5412. To maximize
performance,do notuse the philosophyof separat-
ing analog and digital grounds for chip. All GND
pinsshouldbe connectedtogetherasclose aspos-
sible to the pins, and the VCC pins should be
strapped together. All ground connections to each
deviceshould meet at a common pointas close as
possibleto the GND pins to prevent the interaction
of ground return currents flowing through a com-
mon bus impedance. Two decouplingcapacitors of
10
μ
F and 0.1
μ
F should be connected from this
common point to VCC pins as close as possible to
the chip. Taking care with the board layout in the
following ways will also help prevent noiseinjection
into the receiver frontend and maximize the trans-
mission performances. Keep the crystal oscillator
componentsaway from the receiver inputsand use
a shieldedgroundplanearoundthesecomponents.
Keep the device, the components connected to
LI+/LI-and the transformer as close possible.Sym-
metricallayoutfor theline interfaceis suggested.
. .
. .
1
98T
2
6
120T
5
8
120T
7
3
62T
4
1.5:1
DEVICE SIDE
(primary)
LINE SIDE
(secondary)
Figure 11:
TransformerDesign.
STLC5412
55/74
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