參數(shù)資料
型號： STLC5412FN
廠商： 意法半導體
英文描述： 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
中文描述： 2B1Q U接口裝置加強與無繩模式
文件頁數(shù)： 47/74頁
文件大?。?/td> 655K
代理商： STLC5412FN
RFS = 1: Transfer
anomalies
from
second
section to first section and viceversa
allowed.
RFS = 0: Transfer
anomalies
section to first section and viceversa
not allowed.
LFS
Localfebe select.
Please report to the figure 10. LFS is useful in
repetor application to transfert or not the crc
anomalies (nebe) of a line section to the febe bit
of the sameline section.
from
second
RFS = 0: The computed febe takes in to account
the local nebe.
RFS = 1: The computed febe does not take in to
account the local nebe.
ConfigurationRegister 7 CR7
After reset:02H
-
-
-
-
-
LOCK
PL2EN
DECT
DECT
DECT = 0: Normal mode
DECT = 1: DECT mode
PL2EN
PL2EN = 0: PLL2remains frozen
PL2EN = 1: PLL2 tracks the phase of the receive
signal.
LOCK
LOCK= 0:no phaserelationbetweenSFSrandFSa
LOCK= 1: The phaseof SFSr andFSa rising edges
is fixed
Configurationregister TXB1
Significantonly when format3 selected.
(
μ
W/DSI Only)
After reset:00H Time slot 0 selected.
-
-
B1X5 B1X4 B1X3 B1X2 B1X1 B1X0
B1X5-B1X0
TransmitB1 Time Slot Assignment
Those bits define the binary number of the trans-
mit B1 channel time-slot on Bx input. Time slot
are numbered from 0 to 63. The register content
is takeninto accountat each frame beginning.
Configurationregister RXB1
Significantonly when format3 selected.
(
μ
W/DSI Only)
After reset:00H Time slot 0 selected.
–
–
B1R5 B2R4 B2R3 B2R2 B2R1 B2R0
B1R5-B1R0
Receive B1 Time Slot Assignment
B1R5-B1R0 bits define the binary number of the
receive B1 channel time-slot on BR output. Time
slot are numbered from 0 to 63. The register con-
tent is taken into account at each frame begin-
ning.
Configuration register TXB2
Significant onlywhen format3 selected.
(
μ
W/DSI Only)
After reset: 01H Time slot 1 selected.
-
-
B2X5 B2X4 B2X3 B2X2 B2X1 B2X0
B2X5-B2X0
Transmit B2 Time Slot Assignment
Those bits define the binary number of the trans-
mit B2 channel time-slot on Bx input. Time slots
are numbered from 0 to 63. The register content
is taken into accountat each frame beginning.
Configuration register RXB2
Significant only when format 3 selected. (
μ
W/DSI
Only)
After reset: 01H Time slot 1 selected.
-
-
B2R5 B2R4 B2R3 B2R2 B2R1 B2R0
B2R5-B2R0
ReceiveB2 Time Slot Assignment
Those bits define the binary number of the receive
B2 channel time-slot on BR output. Time slot are
numbered from 0 to 63. The register content is
takenintoaccountat eachframebeginning.
Configuration register TXD
Significant only when format 3 is selectedwith the
D channelselected in the multiplexedmode.
After reset:
μ
W mode 08H (sub time slot 0, time slot 2 se-
lected)
DX5
DX4
DX3
DX2
DX1
DX0
SX1
SX0
DX5-SX0
Transmit D channel Time Slot Assign-
ment
DX5-DX0 and SX1-SX0 bits define the binary
number of the transmit D channel time-slot. DX5-
DX0 bits define the binary number of the 8 bits
wide timeslot. Time slot are numbered from 0 to
63. Within this selected time slot, SX1,SX0 bits
define the binary number of the 2 bits wide time-
slot.Sub time-slots arenumbered 0 to 3. The reg-
ister content is taken into account at each frame
beginning.
Configuration register RXD
Significant only when format 3 is selectedwith the
D channelselected in multiplexedmode.
After reset:
μ
W mode 08H (sub time slot 0, time slot 2 se-
lected)
DR5
DR4
DR3
DR3
DR2
DR1
SR1
SR0
STLC5412
47/74
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