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參數(shù)資料
| 型號： | STLC5412FN |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE |
| 中文描述： | 2B1Q U接口裝置加強與無繩模式 |
| 文件頁數(shù)： | 45/74頁 |
| 文件大?。?/td> | 655K |
| 代理商： | STLC5412FN |
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RR = 1:
UID activation/deactivation complies
with
the
requirements for
equipment. ”LT” or ”NT” behaviour is
selected by means of bit NTS. BP1
and BP2 break-points should be set
equal one too. See state matrix for the
detailed behaviour of UID in this mode
of operation.
repetor
ConfigurationRegister 3 (CR3)
After reset:00H
LB1
LB2
LBD
DB1
DB2
DBD
TLB
T15D
LB1, LB2, LBD
Lineside Loopbackselect.
When set high they turn each individual B1, B2,
or D channel from the Line receive input to the
Line transmit output. They may be set separately
or together.The loopback is operated close to Bx
and Br (or Dx and Dr if the D port is selected).
These loop backs ensures channelsintegrity.
DB1, DB2, DBD
Digital side Channel Loopback
select.
When set high they turn each individual B1, B2,
or D channel from the Digital Interface receive in-
put to the Digital Interface transmit output. They
may be set separately or together. The loopback
is operated close to Bx and Br (or Dx and Dr if D
port selected). These loop backs ensures chan-
nels integrity whatever the selected format or as-
signed channelstime slot.
TLB
TransparentLoopbackselect
TLB = 0: Digital loopbacks are non transparent.
When line side loopback is set, data
transmitted onto the digital interface is
forced to
one. When
loopback is set, data transmitted onto
the line is forced to 1 in NT mode and
to 0 in LT mode.
TLB = 1: 2B+D
is
transparently
throughthe UID.
T15D
Timer15 seconddisabled
digital side
transferred
T15D = 0: On-chip 15 second timer (timer 4 or 5
of ANSI standard) is enabled and
ensure full reset of the activation
procedure
synchronization of the line within 15
second.
T15D = 1: On-chip 15 second timer is disabled.
This means for instance that UID may
attempt to synchronize for ever.
in
case
of
non
Configuration Register 4 (CR4)
After reset: E0H
EB1
EB2
ED
FFIT
ESFr CTLIO MOB
CTC
EB1
B1 channelEnabling
EB1 = 1: Selected B1 channel time-slot on the
DSI/GCI interface is enabled.Note that
transparency of B1 channel remains
under control of the activation state
machine and the ETC bit in CR2.
EB1 = 0: Selected B1 channel time-slot on the
DSI/GCI interface is disabled: Br output
remains in high impedance state and
data on Bx input is ignored. Ones (NT)
or zeroes (LT) are transmitted on the
line.
EB2
B2 channel Enabling Identical to EB1 bit but
for B2 channel.
ED
D channel enabling identical to EB1 but for D
channel on Bx/Br pin or DX/Dr pin depending on
DEN bit inCR2 register.
FFIT
FIFOs interrupt.
FFIT = 1: overflow or underflow of the TXFIFO
and RXFIFO are reported in STATUS
register. An interrupt is generated in
μ
W mode, a MONITOR message is
automaticallysent in GCI mode.
FFIT = 0: No interrupt or message is generated
when FIFOs overflow or underflow.
ESFr
EnableSFSr on pin 25 (40)
ESFr = 0:LSD outputis selected on pin 25 (40).
ESFr = 1:SFSroutput is selectedon pin25 (40).
CTLIO
ControlIO (significant in GCImode only)
CTLIO = 1: The input pins configurated via CR5
register generate a message on
every change even if the UID is
powered down in master mode; that
is to say UID is able to wake up
itself, to provide the clocks, to sends
the message. After that UID is
automatically powered down except
if a PUPcommand is sent to it.
CTLIO = 0: In master mode and powered down,
the UID does not react to an input
pin change.
MOB
MaskOverheadBits.
MOB = 0: No Mask on overheadbit interrupts.
STLC5412
45/74
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