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參數(shù)資料
| 型號(hào)： | STLC5412FN |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE |
| 中文描述： | 2B1Q U接口裝置加強(qiáng)與無繩模式 |
| 文件頁數(shù)： | 26/74頁 |
| 文件大小： | 655K |
| 代理商： | STLC5412FN |
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If not programmed this bit is inactive. The relock
will take place only after completion of present
monitor transfer.(EOM received). This locking will
cause a phasejump of FSa and BCLK signals. To
avoid problems on the GCI bus that is synchro-
nized by FSa, a numberof 5 GCI frames after the
phase jumpwill be ignored by the STLC5412.
For proper system operation before writing the
LOCK bit in CR7 register, the MOB bit (Mask
Overhead Bits) in CR4 register should be set to 1
to avoid spontaneous monitor message genera-
tion from STLC5412. Following the relocking the
MOB bit should be set back to desired value after
a minimum time to be defined(ex. 1msec).
ThesuggestedprocedureistoprogramtheLOCKbit
in CR7
register after the AI indication from
STLC5412.In this case the system controller knows
whenthe phase jump takes placeand can reset the
transmission/receptionoftheGCIcontroller.
Notes:
The DECT EOC message reception generatesan
interrupt as a normal EOC message according to
the rules stored in OPR register. The DECT sync
message must be checked 3 times (reset value
of OPR register). If it is not detected3 times iden-
tical no pulse is generated. The DECT pulse
width on output pin SFSx is 6msec.
MAINTENANCE FUNCTIONS
M channel
In each frame there are 6 ”overhead”bits assigned
to various control and maintenance functions.
Some programmable processing of these bits is
provided on chip while interaction with an external
controller provides the flexibility to take full advan-
tage of the maintenance channels. See OPR,
TXM4, TXM56, TXEOC,RXM4, RXM56, RXEOC
TX EOC
SFSx
n*12ms (n=40 minimum)
6 ms
DECT DECT DECT
txeoc
txeoc
txeoc
txeoc
txeoc
txeoc
txeoc
txeoc
txeoc
DECT
DECT
DECT
LT DECT MODE
NT DECT MODE
SFSx
n*12ms
RX EOC
12 ms
SFSr
RXEOC INT
RXEOCINT
RXEOCINT
RXEOCINT
6 ms
DECT DECT
DECT
rxeoc
rxeoc
rxeoc
rxeoc
rxeoc
rxeoc
rxeoc
rxeoc
rxeoc
DECT
DECT
DECT
36ms + line delay
TIMING DIAGRAMS FOR DECT
STLC5412
26/74
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