參數(shù)資料
型號： STLC5412FN
廠商： 意法半導(dǎo)體
英文描述： 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
中文描述： 2B1Q U接口裝置加強與無繩模式
文件頁數(shù)： 15/74頁
文件大?。?/td> 655K
代理商： STLC5412FN
To reada 12 bits message,the difference is:
limited addressfield:
extended data field (D11 - D8): A3 - A0.
The Write/Readback indicator doesn‘t exit.
A7- A4
DIGITAL SYSTEM INTERFACE
Two B channels,eachat 64 kbit/s andone D chan-
nel at 16 kbit/s form the Basic access data. Basic
accessdata is transferredon the Digital System In-
terface with several different formats selectable by
meansof theconfigurationregisterCR1.
The DSI is basically constituted of 5 wires (see
fig.2 and 3):
BCLK
Bx
Br
FSa
FSb
bit clock
data input to transmitto the line
data output received from the line
Transmit Frame sync
ReceiveFrame sync
It is possibleto separatethe D channelfrom the B
channels and to transfer it on a separate Digital
Interfaceconstitutedof 2 pins:
Dx
Dr
D channel data input
D channel data ouput
The TDM (Time Division Multiplex) mode uses
the same bit and frame clocks as for the B chan-
nels. The continuous mode uses an internally
generated 16 kHz bit clock output:
DCLK
D channel clock output
For all formats when D channel port is enabled
”continuous mode” is possible. When the D chan-
nel port is enabled in TDM mode, D bits are as-
signed according to the related format on Dx and
Dr .
STLC5412 provides a choice of four multiplexed
formats for the B and D channels data as shown
in fig.2 and 3.
Format 1:
the 2B+D data transfer is assigned to
the first 18 bits of the frame on Br and Bx I/0 pins.
Channels are assigned as follows: B1(8 bits),
B2(8 bits), D(2 bits), with the remaining bits ig-
nored until the next Frame syncpulse.
Format 2:
the 2B+D data transfer is assigned to
the first 19 bits of the frame on Br and Bx I/O
pins. Channels are assigned as follows: B1(8
bits), D(1 bit), 1 bit ignored, B2(8 bits), D(1 bit),
with the remaining bits ignored until the next
framesync pulse.
Format 3:
B1 and B2 Channels can be inde-
pendently assigned to any 8 bits wide time slot
among 64 (or less) on the Bx and Br pins. The
transmit and receive directions are also inde-
pendent. When TDM mode is selected, the D
channel can be assigned to any 2 bits wide time
slot among 256 on the Bx and Br pins or on the
Dx and Dr pins (D port disabled or enabled in
TDM mode respectively).
Format 4:
is a GCI like format excluding Monitor
channel and C/I channel. The 2B+D data transfer
is assigned to the first 26 bits of the frame on Br
and Bx I/O pins. Channels are assigned as fol-
lows. B1(8 bits) B2(8 bits), 8 bits ignored, D(2
bits), with remaining bits ignored up to the next
frame syncpulse.
When the Digital Interface clocks are selected as
inputs, FSa must be a 8 kHz clock input which in-
dicates the start of the frame on the data input pin
Bx. When the Digital Interface clocks are selected
as outputs, FSa is an 8 kHz output pulse con-
forming to
the selected format which indicates
the frame beginning for both Tx and Rx direc-
tions.
When the Digital Interface clocks are selected as
inputs, FSb is a 8 kHz clock input which defines
the start of the frame on the data ouput pin Br.
When the Digital Interface clocks are selected as
outputs, FSb is a 8 kHz output pulse indicating
the second 64kbit/sslot.
Two phase-relations between the rising edge of
FSa/FSb and the first (or second for FSb as out-
put) slot of the frame can be selected depending
on format selected: Delayed timing mode or non
Delayed timing mode.
Non delayed data mode is similar to long frame
timing on the COMBOI/II series of devices: The
first bit of the frame begins nominally coincident
with the rising edge of FSa/b. When output, FSa
is coincident with the first 8 bits wide time-slot
while FSb is coincident with the second 8 bits
wide time-slot. Non delayed mode is not available
in format 2.
Delayed timing mode, which is similar to short
frame sync timing on COMBO I/II, in which the
FSa/b input must be set high at least a half cycle
of BCLK earlier the frame beginning. When out-
put, FSa 1bit wide pulse indicates the first 8 bits
wide time-slot while FSb indicates the second.
Delayed mode is not availablein format4.
2B+D basic access data to transmit to the line
can be shifted in at the BCLK frequency on the
falling edges during the assigned time-slots.
When D channel port is enabled, only B1 & B2
data is shiftedin duringthe assignedtime slots. In
format 4, data is shifted in at half the BCLK fre-
quencyon the receivefalling edges.
2B+ D basic access data received from the line
can be shiftedout from the Br output at the BCLK
frequencyon the rising edges during the assigned
time-slots. Elsewhere, Br is in the high impedance
state. When the D channel port is enabled, only
B1 & B2 data is shifted out from Br. In Format 4,
data is shifted out at half the BCLK frequency on
the transmit rising edges; there is 1.5 perioddelay
between the rising transmit edge and the receive
falling edge of BCLK.
STLC5412
15/74
相關(guān)PDF資料
PDF描述
STLC5412P 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
STLC5444 Quad Feed Power Supply(ISDN四饋電電源)
STLC5460 Line Card Interface Controller(線路卡片接口控制器)
STLC7546 MODEM (V.34bis) Analog Front End(調(diào)制解調(diào)器模擬前端)
STLC7550TQFP LOW POWER LOW VOLTAGE ANALOG FRONT END
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
STLC5412P 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
STLC54155 功能描述:電信集成電路 155MBit Coaxial Intr RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray
STLC5432 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
STLC5432Q 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
STLC5444 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:QUAD FEEDER POWER SUPPLY
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*