參數(shù)資料
型號(hào)： STLC5412
廠商： 意法半導(dǎo)體
英文描述： 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
中文描述： 2B1Q U接口裝置加強(qiáng)與無繩模式
文件頁數(shù)： 63/74頁
文件大小： 655K
代理商： STLC5412
TIMING CHARACTERISTICS
Symbol
MASTER CLOCK
Parameter
Test Condition
Min.
Typ.
Max.
Unit
FMCLK
Frequency of MCLK
Tolerance
MCLK/XTAL Input Clock Jitter
Clock Pulse Width, MCLK High Level
Clock Pulse Width, MCLK Low Level
Rise Time of MCLK
Fall Time of MCLK
DIGITAL INTERFACE
Including Temperature,
Aging, Etc...
External Clock Source
V
IH
= V
CC
– 0.5V
V
IL
= 0.5V
–100
15.36
+100
50
MHz
ppm
nspk-pk
ns
ns
ns
ns
tWMH
tWML
tRM
tFM
20
20
Used as a Logic Input
10
10
FBCLK
Frequency of BCLK
Formats 1, 2 and 3
Format 4 and GCI Mode
Measured from V
IH
to V
IH
Measured from V
IL
to V
IL
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
DSI or GCI Slave Mode only
DSI or GCI Slave Mode only
DSI orGCI Master Mode only
Load=150pF+2LSTTLLoads
256
512
30
30
4095
6144
KHz
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWBH
tWBL
tRB
tFB
tSFB
tHBF
tDBF
tDBD
tDBDZ
tDFD
tSDB
tHBD
tDBT
tDBTZ
tDFT
D PORTIN CONTINUOUS MODE: 16KBITS/SEC
Clock Pulse Width, BCLKHigh Level
Clock Pulse Width, BCLKLow Level
Risae Time of BCLK
Fall Time of BCLK
SetupTime,FSHighorLowtoBCLKLow
Hold Time,BCLKLowto FSHighor Low
Delay Time,BCLK HightoFSHighorLow
Delay Time, BCLK High to Data Valid
Delay Time, BCLK High to Data HZ
Delay Time, FS High to Data Valid
Setup Time, Data Valid to BCLK Low
Hold time, BCLK to Data Invalid
Delay Time, BCLK High to TSR Low
Delay Time, BCLK Low to TSR HZ
Delay Tie, FS High to TSR Low
15
15
30
20
–20
20
80
50
80
Load=150pF+2LSTTLLoads
0
20
Load=100pF+2LSTTLLoads
80
50
80
Load=100pF+2LSTTLLoads
tSDD
tHDD
tDDD
MICROWIRE CONTROL INTERFACE
SetupTime,DCLKLowtoDX HighorLow
Hold Time,DCLK Lowto DX High orLow
Delay Time,DCLK HightoDRHighorLow
50
50
ns
ns
ns
Load = 50pF + 2LSTTLLoads
80
FCCLK
tWCH
tWCL
tRC
tFC
tSSC
tHCS
tWSH
tSIC
tHCI
tDSO
tDCO
tDCOZ
tDCI
Frequency of CCLK
Clock Pulse Width, CCLK High Level
Clock Pulse Width, CCLK Low Level
Rise Time of CCLK
Fall Time of CCLK
Setup Time, CSB Low to CCLK High
Hold Time, CCLK Low to CSB High
Duration of CSB High
Setup Time, CI Valid to CCLK High
Hold Time, CCLK High to CI Invalid
Delay Time, CSB Low to CO Valid
Delay Time CCLK Low to CO Valid
Delay Time, CCLK Low to CO HZ
Delay Time,CCLK LowtoINTBLoworHZ
5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Measured from V
IH
to V
IH
Measured from V
IL
to V
IL
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
85
85
15
15
60
10
200
25
25
Out FirstBit on CO
Load = 50pF + 2LSTTLLoads
50
50
50
150
Load = 80pF+ 2LSTTLLoads
STLC5412
63/74
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