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參數(shù)資料
| 型號： | STLC5412 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE |
| 中文描述： | 2B1Q U接口裝置加強(qiáng)與無繩模式 |
| 文件頁數(shù)： | 51/74頁 |
| 文件大?。?/td> | 655K |
| 代理商： | STLC5412 |
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MWPS Micro Wire Port Select register (Signifi-
cant in microwiremode only).
(write only)
Default value: Mode A (5410 compatible)
– Writting FFH value select the mode B to ex-
changedata ontoCI & CO
– Writing 00H value select the mode A (See Mi-
crowire control interface paragraph for more
detailsMode A, Mode B).
Note: Soft Reset has no effect on the select
mode.
BAUD DELAY Register (DBAUD)
After reset:00H
DBAUD7 DBAUD6 DBAUD5 DBAUD4 DBAUD3 DBAUD2 DBAUD1 DBAUD0
8 bits read-only register that provides the round
trip bauds delay (12.5usecstep). It is significantin
LT modeonly. The register is split in two sections:
DBAUD4..DBAUD0: 5 bits counterof bauds delay
between SFSx and SFSr rising edges (
total digi-
tal delay: tdd
).
DBAUD7..DBAUD5: 3 bits to store the internal
elastic memory (FIFO) state. The table A shows
the coding of the 3-stages elastic memory (
elas-
tic digital delay:edd
).
Table A.
FIFO state
000
010
110
baud delay (edd)
-1
-2
0
-2: 2 bauds have to be subtracted from bauds
countervalue (DBAUD4..DBAUD0)
-1: 1 baud has to be subtracted to bauds counter
value (DBAUD4..DBAUD0)
0: no correction
All other FIFO states are used during activation
procedure. Once PLL2 is frozen you can be only
in one of the 3 statesin tableA.
TX RX Clocks Different Register(DTXRX)
After reset: 00H
7
6
5
4
3
2
1
0
8bits read-only register that provides the phase
difference between transmit clock and receive re-
covered clock by PLL2 in steps of 65.1 nsec.
(
clock elastic delay: ced
). The register is signifi-
cant in LT mode only.
STLC5412
51/74
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