參數資料
型號： STLC5412
廠商： 意法半導體
英文描述： 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
中文描述： 2B1Q U接口裝置加強與無繩模式
文件頁數： 29/74頁
文件大?。?/td> 655K
代理商： STLC5412
Table 4:
NT-to-Network 2B1Q SuperframeTechnique and Overhead Bit Assignments.
FRAMING
1-9
1-18
2B+D
10-117
19-234
Overhead Bits (M
1-
M
6
)
119s
237
Quat Positions
Bit Positions
Basic
Frame
#
1
2
3
4
5
6
7
8
118s
235
118m
236
119m
238
120s
239
120m
240
Super
Frame
#
1
Sync Word
ISW
SW
SW
SW
SW
SW
SW
SW
2B+D
2B+D
2B+D
2B+D
2B+D
2B+D
2B+D
2B+D
2B+D
M
1
eoc
a1
eoc
dm
eoc
i3
eoc
i6
eoc
a1
eoc
dm
eoc
i3
eoc
i6
M
2
eoc
a2
eoc
i1
eoc
i4
eoc
i7
eoc
a2
eoc
i1
eoc
i4
eoc
i7
M
3
eoc
a3
eoc
i2
eoc
i5
eoc
i8
eoc
a3
eoc
i2
eoc
i5
eoc
i8
M
4
act
ps
1
ps
2
ntm
cso
1
sai
1
M
5
1
1
crc
1
crc
3
crc
5
crc
7
crc
9
crc
11
M
6
1
febe
crc
2
crc
4
crc
6
crc
8
crc
10
crc
12
2,3,...
NT-to-Network superframedelayoffset from Network-to-NT superframeby 60
±
2 quats (about 0.75 ms).
All bits than the Sync Word are scrambled.
Symbols & Abbreviations:
”1”
reserve = reserved bit for future standard; set = 1
ps
1
,
ps
2
ntm
power status bits (set = 0 to indicate power
problems)
NT in Test Mode bit (set = 0 to indicate test mode
eoc
embedded operations channel
a = address bit
dm = data/message indicator
i = information (data/message)
synchronization word
inverted synchronization word
SW
ISW
cso
crc
cold-start-only bit (set = 1 to indicatecold-start-only
cyclic redundancy check: covers 2B+D & M4
1 = most significantbit
2 = next most significant bit
etc
far end block errorbit (set = 0 for errored
superframe)
S/T interface activation indication bit.
s
sign bit(first) in quat
febe
m
act
magnitude bit (second) in quat
activation bit
sai
Figure 6
: Exampleof 2B1Q QuaternarySymbols.
STLC5412
29/74
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