參數(shù)資料
型號(hào)： STLC5412
廠商： 意法半導(dǎo)體
英文描述： 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
中文描述： 2B1Q U接口裝置加強(qiáng)與無繩模式
文件頁數(shù)： 27/74頁
文件大?。?/td> 655K
代理商： STLC5412
registers description for details. New data written to
any of the overhead bit Transmit Registers is resyn-
chronized internally to the next available complete
superframeorhalfsuperframe,asappropriate.
Embedded Operation Channel (EOC)
The eoc channel consists of two complete 12 bits
messagesper superframe,distributedthrough the
M1, M2 and M3 bits of each frame. Each mes-
sage is composed of 3 fields; a 3 bit address
identifying the message destination/origin, a 1 bit
indicator for the data mode i.e. encoded message
or raw data, and an 8 bits information field. The
Control Interface(Microwire or Monitor channel in
GCI) provides access to the complete 12 bits of
every message in TX and RX EOC registers.
When non-automode is selected,UID does not in-
terpret the received eoc messages e.g. ”send cor-
rupted CRC”; therefore the appropriate command
instructionmust be written to the device e.g. ”set to
one bit CTC in register CR4”. It is possible to select
a transparenttransmission mode in which the eoc
channelcanbe consideredas atransparent2 kbit/s
channel.See OPRregisterdescriptionfordetails.
When auto-mode is selected in GCI configuration,
UID performs automatic recognition / acknow-
ledgement of the eoc messages sent by the net-
work according to processing defined in ANSI
standard and illustrated in figure 9. When UID rec-
ognizes a message with the appropriate address
and a known command, it performs automatically
the relevant action inside the device and send a
message at the digital interfaceas appropriate.Ta-
ble 5givesthe list of recognizedeoc messagesand
associatedactions.
When NT-RR-AUTO configuration is selected,
eoc addressingis processed according to appen-
dix E of T1E1.601standard:
– If address of the eoc message received from
LT is in the range of 2 to 6, UID decrements
address and pass the message onto GCI.
– If address of the eoc message received from
GCI is in the range of 1 to 5, UID increments
address and pass the message onto the line
toward LT.
– If data/msg indicator is set to 0, UID pass
data on transparentlywith eoc address as de-
scribed above.
M4 channel
M4 bit positions of every frame is a channel in
which are transmitted data bits loaded from the
TXM4 transmit register and from the on-chip acti-
vation sequencer each superframe. On the re-
ceive side, M4 bitsfrom one complete superframe
are first validated and then stored in the RXM4
Receive Register or transmitted to on-chip activa-
tion sequencer. See OPR, TXM4 and RXM4 reg-
isters descriptionfor details.
When NT1-AUTO or NT-RR-AUTO mode is se-
lected, bits ps1 and ps2 in M4 channel are con-
trolled directly by biasing input pins ES1 and ES2
respectively. e.g. ps1 is sent continuously to the
line equal 0 when ES1 input is forcedat 0 Volt.
Spare M5 and M6 bits
The spare bit positions in the M5 and M6 field
form a channel in which are transmitted data bits
loaded from the TXM56 transmit register. On the
receive side, the spare bits in the M5 and M6
field are first validated and then stored in the
RXM56 receive register. See OPR, TXM56 and
RXM56 registers description for details.
CRC calculation/checking
In transmit direction, an on-chip CRC calculation
circuit automaticallygenerates a checksum of the
2B+D+M4 bits using the specified 12th order
polynomial. Once per superframe, the CRC is
transmitted in the M5 and M6 bit positions. In re-
ceive direction, a checksum is again calculated
on the same bits as they are received and, at the
end of the superframe compared with the re-
ceived CRC. The result of this comparison gener-
ates a ”Far End Block Error” bit (febe) which is
transmitted back towards the other end of the
Line in the next but one superframe and an indi-
cation of Near End Block Error is sent to the sys-
temby means of RegisterRXM56. If there is no er-
ror insuperframe,febeis set= 1, andif thereis one
ormore errors, febeis set= 0.
UID also includes two 8 bits Block Error Counters
associated with the febe bits transmitted and re-
ceived. It is then possible to select one Error
Counter per direction or to select only one counter
forbothby means of bit C2E in OPRregister.Block
errorcountingis always enabledbutit is possibleto
disabled the threshold interrupt and/or to en-
able/disablethe interrupt issuedat eachreceivedor
transmittedblock error detection.See OPR register
fordetails.
Loopbacks
Six transparent or non transparent channel loop-
backsare providedby UID. Itis thereforepossible to
operateany loopbackon B1, B2 andD channelsline
to line or DSI/GCI to DSI/GCI. Command are
groupedinCR3register.
In addition to the channel loopbacks in LT modes,
a complete transparent loopback operated at the
transmission side of UID allows the device to acti-
vate through an appropriate sequence with the
complete data stream looped-back to the re-
ceiver. Therefore,most of analog/digitalclock and
data recovery circuits are tested. After activation
completed, an AI status indication is reported.
Complete loopbackis enabledwith ARL command
in TXACT register.
STLC5412
27/74
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