參數(shù)資料
型號(hào)： STLC5411P
廠商： 意法半導(dǎo)體
英文描述： 2B1Q U INTERFACE DEVICE
中文描述： 2B1Q U接口裝置
文件頁數(shù)： 41/72頁
文件大?。?/td> 739K
代理商： STLC5411P
eas:
area 00/0FH: NOP operations.
area 10/1FH: test registers:reserved.
area 20/2FH: the configurationregisters.
OPR CR1 CR2 CR3 CR4 CR5
CR6
Read Write access. CR5 only
usefull in GCI mode
area 30/3FH: the B1 B2 D time slot registers.
TXB1 TXB2RXB1 RXB2 TXD
RXD STATUS
Read Write access except
STATUS: Read only.
Usefull only in MW mode
except STATUS: MW & GCI
modes.
area 40/4FH: the transmit and receive
registers (except EOC).
TXM4 RXM4 TXM56 RXM56
TXACT RXACT BEC1 BEC2
ECT1ECT2 RXOH
Read Write access for the
transmitregisters:
TXM4 TXM56 TXACT
Read access only for the
receiveregisters:
RXM4 RXM56 RXACT
Read Write access for the
control registers:
ECT1 ECT2
Read access only for the error
registers:
BEC1 BEC2
Write accessonly for the
commandregisters:
RXOH
area5x to 9x:
5x:
to write TXEOC register, to read
RXEOC register.
to read TXEOCregister.
reserved
to read IDR register.
reserved.
reserved except FF address:
special registerMWPS.
6x:
7x:
8x &9x:
areaAxtoEx:
area Fx:
for 12bits registers.
Overhead bitsprogrammableregister
(OPR)
After reset: 1EH
CIE
CIE
Near-EndCRC Interrupt Enable:
EIE
FIE
OB1
OB0
OC1
OC0
C2E
CIE = 1: the RXM56 register is queued in the
interrupt registerstack with nebe bit
set to zero each time the CRCresult
is not identical to the corresponding
CRC received from the line.
CIE = 0: no interruptis issued but the error
detectionremains active for instance
for on chip error counting.
EIE
Error counting InterruptEnable:
EIE = 1: an interrupt is provided for the
counterwhen the threshold(ETC1 or
ETC2) is reached.
EIE= 0:
no interrupt is issued. It isfeasible to
read the counterseven if no relevant
interrupt has been provided.
FIE
FEBE lnterrupt Enable:
FIE = 1:
the RXM56registeris queuedinto
the interruptregister stack each time
the febebit is received at zeroin a
superframe.
no interruptis issuedbut the receive
febe bit remains active for on chip
error counting.
FIE = 0:
OB1, OB0
Overhead Bit processing:
select how eachspare overheadbit received from
the line is validated and transmitted to the sys-
tem. RXM4 and RXM56 registers are inde-
pendently provided onto the system interface as
for the eoc channel. Each spare overhead bit is
validated independentlyfrom the others.
OB1
0
OB0
0
each super frame, an interrupt
is generated for the RXM4 or
the RXM56 register. Spare bits
are transparently transmited to
thesystem.
an interrupt is set at each new
spare overhead bit(s) received.
an interrupt is set at each new
spare overhead bit(s) received
and confirmed once. ( two
times identical).
an interrupt is set at each new
spare overhead bit(s) received
and confirmed twice. (three
times identical).
0
1
1
0
1
1
If new bits are received at the same time in M4
STLC5411
41/72
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