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參數(shù)資料
| 型號： | STLC3065 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | WLL SUBSCRIBER LINE INTERFACE CIRCUIT |
| 中文描述： | 環(huán)路用戶線路接口電路 |
| 文件頁數(shù)： | 11/27頁 |
| 文件大小： | 194K |
| 代理商： | STLC3065 |
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Depending on the P1,P2 control bits the ring
waveform can be applied to both 2W ports
(TIP1/RING1 and TIP2/RING2) or to one of the
two(see also table2).
The ring trip detection is performed sensing the
variation of the AC line impedance from on hook
(relatively high) to off-hook (low). This particular
ring trip method allows to operate without DC off-
set superimposed on the ring signal and therefore
obtaining the maximum possible ring level on the
load starting from a givennegative battery.
It should be noted that such a method is opti-
mised for operationon shortloop applicationsand
may not operateproperly in presenceof long loop
applications(>500
).
Once ring trip is detected,the DET output is acti-
vated (logic level low), at this point the card con-
troller or a simple logic circuit should stop the D2
toggling in order to effectively disconnect the ring
signal and then set the STLC3065 in the proper
operatingmode (NormallyACTIVE).
RING LEVEL IN PRESENCE OF MORE TELE-
PHONE IN PARALLEL.
As already mentioned above the maximum cur-
rent that can be drawn from the Vpos supply is
controlledand limited via theexternalRSENSE.
This will limit also the power available at the self
generatednegative battery.
If for any reason the ringer load will be too high
the self generated battery will drop in order to
keep the power consumption to the fixed limit and
therefore also the ring voltage level will be re-
duced.
In the typical applicationwith RSENSE = 110mW
the peak current from Vpos is limited to about
900mA, which correspond to an average current
of 700mA max. In this condition the STLC3065
can drive up to 3REN with a ring frequency
fr=25Hz (1REN = 1800
+ 1.0
μ
F, European
standard).
In order to drive up to 5REN (1REN= 6930
+
8mF, US standard) it is necessary to modify the
externalcomponentsas follows:
CREV= 15nF
RD = 2.2 K
Power On Requirements
In order to avoid damage to the device when
Vpos is firstapplied it is recommended to keep all
the logic inputs to a low logic level (0V) until Vpos
is > 5.5V.
In case this power up sequence cannot be guar-
anteed,it’s recommended to connect a shottkydi-
ode (BAT46 or equivalent) between VBAT and
BGND (see figure 7).
LayoutRecommendation
A properly designed PCB layout is a basic issue
to guarantee a correct behaviourand good noise
performances.
Particular care must be taken on the ground con-
nection and in this case the star configuration al-
lows surely to avoid possibleproblems (see Appli-
cationDiagramFig. 8).
The ground of the power supply (VPOS) has to
be connected to the center of the star, let’s call
this point PGND. This point should show a resis-
tance as low as possible, that means it should be
a ground plane.
Noise sources can be identified in not enough
good grounds, not enough low impedance sup-
plies and parasitic coupling between PCB tracks
and high impedance pins of the device.
In particular, to avoid noise problems,
should prevent any coupling between the DC/DC
converter components and analog pins that are
referred to AGND (ex: RD, IREF, RTH, RLIM,
VF). As a first reccomendation the components
CV, L, D1, CVPOS, RSENSE should be kept as
close as possible to each other and isolated from
theother components.
Additionalimprovements can be obtained:
decoupling the center of the star from the analog
groundof STLC3065 usingsmall chokes.
adding a capacitor in therange of 100nFbetween
VPOS and AGND in order to filter the switch fre-
quencyon VPOS.
layout
BAT46
BGND
VBAT
STLC3065
Figure 7. Shottkydiode connection
STLC3065
11/27
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