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參數(shù)資料
| 型號(hào)： | STLC3065 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | WLL SUBSCRIBER LINE INTERFACE CIRCUIT |
| 中文描述： | 環(huán)路用戶線路接口電路 |
| 文件頁(yè)數(shù)： | 10/27頁(yè) |
| 文件大?。?/td> | 194K |
| 代理商： | STLC3065 |
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As already mentioned the metering pulse echo
cancellation is obtained by means of two external
components(RTTX and CTTX) that should match
the line impedance at the TTX frequency. This
simple networkhas a double effect:
Synthesise a low output impedance at the
TIP/RINGpins at the TTX frequency.
Cut the eventual TTX echo that will be trans-
ferredfrom the line to theTX output.
Ringing
D0
D1
D2
P1
P2
DET
DET1
DET2
1
0
0/1
@fr
1
1
RTrip
line 1+2
disable
disable
1
0
0/1
@fr
0
1
RTrip
line 2
disable
disable
1
0
0/1
@fr
1
0
RTrip
line 1
disable
disable
When this mode is selected STLC3065self gen-
erate an higher negative battery (-70V typ.) in or-
der to allow a balanced ringing signal of typically
62Vpeak.
The SLIC core is set in ring mode via the control
inputsD0 andD1 setrespectively to 0 and 1.
In this condition both the DC and AC feedback
loop are disabled and the SLIC core line drivers
operateas voltagebuffers.
The ringwaveform is obtainedtogglingthe D2 con-
trol bit at the desiredring frequency.This bit in fact
controlsthelinepolarity(0=direct;1=reverse).
As in the ACTIVE mode the line voltage transition
is performed with a ramp transition, obtaining in
this way a trapezoidal balanced ring waveform
(seefig.6).
The shaping is defined by the CREV external
capacitor.
Selecting the proper capacitor value it is possible
to get different crest fattor values. The following
table shows the crest factor values obtained with
a 20Hz and 25Hz ring frequency and with 1REN.
This value are valid either with European or USA
specification:
CREV
CREST
FACTOR
@20Hz
CREST
FACTOR
@25Hz
22nF
1.2
1.26
27nF
1.25
1.32
33nF
1.33
Not significant (*)
(*)Distorsion already less than 10%.
CTTX1
CTTX2
CS
RLV
SQTTX
RLV
BURST
SHAPING
GENERATOR
D0
CKTTX
Square wave pulse metering
Sinusoidal wave
pulse metering
RTTX
FTTX
Low Pass Filter
-
+
OP1
CFL
R1
R2
C2
C1
Required external components vs. filter order.
Figure 5. Meteringpulse generation circuit.
Order CFL
R1
C!
R2
C2
THD
1
X
13%
2
X
X
X
X
6%
3
X
X
X
X
X
3%
GND
TIP
RING
VBAT
dV/dT set
by CREV
2.5V typ.
65V
typ.
2.5Vtyp.
Figure 6. TIP/RINGtypical ringing waveform
STLC3065
10/27
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