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參數(shù)資料
| 型號： | STLC1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LED LAMPS CLUSTER DRIVER |
| 中文描述： | LED節(jié)能燈驅(qū)動集群 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 298K |
| 代理商： | STLC1 |
STLC1
6/16
ELECTRICAL CHARACTERISTICS FOR FEEDBACK AND CONTROL
(T
J
=-40 to 125°C unless
otherwise specified. Typical values are referred at T
J
=25°C, V
B+
=14V)
Note 1: The device is powered. If only one of the three inputs is enabled (the remaining inputs are shorted to ground), t
SMPS-ON
is the time
required for the OUT voltage to reach the10% of its own steady state value
Note 2: The device is powered. If only one of the three inputs is brought high (the remaining inputs are shorted to ground), T
LSD-ON
is the
time required for the current to flow in the enabled LSD
Note 3: The device is powered and at least one input is enabled. If this input is disabled, T
LSD-OFF
is the time required for the current to be-
come zero in the previously enabled LSD.
Note 4: Guaranteed by design, not tested in production.
FUNCTIONAL DESCRIPTION
SMPS
The
grounded, thus it is possible to use any converter
configuration with the power switch connected to
ground. A SEPIC topology (Single Ended Primary
Inductor
Current)
is
application schematic.
N-channel
Power
MOSFET
is
source
shown
in
the
typical
INPUTS PINS
The IC’s inputs are TURN, STOP and TAIL. If all
inputs are disabled, SMPS and most of the
internal control and diagnostic circuitry are not
active. This is done in order to maintain the
stand-by quiescent current at very low values.
When only one of these inputs is put high (e.g
connected to V
B+
), a device start-up phase
begins. First the C
REF
capacitor is charged and,
once the voltage on it has reached about 95% of
its steady state value (V
REF
), the SMPS is
enabled. In order to allow the output to reach the
regulated
voltage
value
corresponding to the input enabled will conduct
faster,
the
LSD
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
LOUT
Lamp Outage Detect
Threshold Voltage
Output Overcurrent
Threshold Voltage
External Voltage
Reference
T
J
=25°C
150
200
250
mV
V
H-SHORT
T
J
=25°C
1.2
1.3
1.6
V
V
REF
V
TURN
= V
STOP
= V
TAIL
= V
B+
I
REF
= 500
μ
A
V
TURN
= V
STOP
=V
TAIL
= V
B+
3.6
3.8
4
V
V
FB
Internal Band-gap Voltage
Reference (see schematic
diagram)
Device Enabled Lamp
Outage no fault High
Voltage
Device Disabled Lamp
Outage no fault High
Voltage
Lamp Outage fault Low
Voltage
TURN, STOP and TAIL
Input Resistance
Thermal Shutdown
Threshold
Thermal Shutdown
Hysteresis
Time to Fault Indication
ON
Time to Fault Indication
OFF
V
TS-PWM(L)
TS-PWM Low State
Voltage (see table 1)
V
TS-PWM(M)
TS-PWM Mid State
Voltage (see table 1)
V
TS-PWM(H)
TS-PWM High State
Voltage (see table 1)
1.15
1.24
1.3
V
V
LH(en)
V
B+
= 9 to 16V, I
LMP-OUT
< -4mA
least one input enabled. No fault
condition.
V
B+
= 9 to 16V, I
LMP-OUT
< -2mA
V
TURN
= V
STOP
= V
TAIL
= 0V
At
V
B+
-2
V
B+
V
V
LH(dis)
V
B+
-2
V
B+
V
V
LL
V
B+
= 9 to 16V I
LMP-OUT
< 100mA
least one input enabled. Fault condition.
V
B+
= 12V,
At
1.5
V
R
(IN)
18.5
k
T
SHDN
(see Note 4)
150
°C
T
HYST
(see Note 4)
10
°C
t
F(on)
60
μ
s
t
F(off)
8
ms
0.1V
REF
V
0.21V
REF
0.79V
REF
V
0.98V
REF
V
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