參數(shù)資料
型號(hào)： STi4600
廠商： 意法半導(dǎo)體
英文描述： 6 Channel Dolby AC-3 MPEG1/2 Audio Decoder(六通道音頻解碼器)
中文描述： 6聲道杜比AC - 3 MPEG1 / 2音頻解碼器（六通道音頻解碼器）
文件頁(yè)數(shù)： 9/52頁(yè)
文件大?。?/td> 321K
代理商： STI4600
9/52
STi4600
INTERNAL CIRCUIT DESCRIPTION
(Cont’d)
3.2 PLL SETUP
There are two embedded PLLs in the STi4600: the
system PLL and the PCM PLL. Both are used to
generate clocks from the 27 MHz clock input.
3.2.1 System PLL
The system PLL is used to create the system clock
from the 27 MHz input clock.This PLL is software
programmable. A register is used to set the fre-
quency between 1.5 MHz up to 33 MHz in steps of
1.5 MHz. After hard reset the system clock is run-
ning at 33 MHz. An RC must be connected to the
filter pin VCSYS, recommended values are 1.5
Kohms / 1nf.
3.2.2 DAC PLL
This PLL is used to generate the clock for the dig-
ital to analog converter. The use of this PLL is op-
tional. After Hard reset this PLL is disabled and the
pin PCMCLK is an input of the device.
To activate this PLL an internal register must be
set. In this case the pin PCMCLK becomes an out-
put.
The
output
clock
384x44.1KHz or 384x48 KHz, the choice is done
via a host register. An RC must be connected to
the filter pin VCDAC, recommended values are 10
Kohms / 2.2nf.
frequency
can
be
相關(guān)PDF資料
PDF描述
STI4600 6 CHANNEL DOLBY AC-3 MPEG1/2 AUDIO DECODER
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