參數(shù)資料
型號(hào): STi4600
廠商: 意法半導(dǎo)體
英文描述: 6 Channel Dolby AC-3 MPEG1/2 Audio Decoder(六通道音頻解碼器)
中文描述: 6聲道杜比AC - 3 MPEG1 / 2音頻解碼器(六通道音頻解碼器)
文件頁數(shù): 30/52頁
文件大?。?/td> 321K
代理商: STI4600
30/52
STi4600
REGISTER DESCRIPTION
(Cont’d)
5.4 REGISTER MANUAL
5.4.1 Version registers
VERSION -
Version
Address
Type
Software Reset:
Hardware Reset:
Description
The VERSION register is read-only and is used to
identify the IC on an application board.
The version register holds the cut number (binary
decimal encoded).
The version numbers are defined as below:
First PQFP120 cut, version number is: 0x10
First PQFP80 cut, version number is: 0x20
:
:
0x00
R0
NA
NA
IDENT -
Identify
Address
Type
Software Reset:
Hardware Reset:
Description
IDENT is a read-only register and is used to iden-
tify the IC on an application board. IDENT always
has the value “0xAC”.
:
:
0x01
RO
NA
NA
SOFTVER -
Software Version
Address
Type
Software Reset:
Hardware Reset:
Description
The SOFTVER register is the version of the micro-
code which is running on the device. This register
is updated just after a soft reset of the device. To-
day this register is not used.
5.4.2 Setup and Inputs
PLLSYS -
System PLL Setup
:
:
0x71
R/W
NC
UND
Address
Type
Software Reset:
Hardware Reset:
:
:
0x11
R/W
NC
0x16
Description
This PLL creates the system clock from the 27
MHz clock input.
The PLL can be bypassed and disabled. The fre-
quency of the system clock is related to the value
of the divider:
SYSCLK= 1.5 MHz *Div Min freq : = 3 MHz, Max
freq should be less or equal to 33 MHz
When a Hardreset occurs the PLL is enabled and
runs at 33 MHz.When a “softreset” occurs this reg-
ister is not changed and the PLL runs as before
the softreset.
BYP
: BYPASS. When set the PLL is by-
passed CLKSYS= CLKIN
DIS
: Disabled. When set the PLL is disa-
bled (not running)
DIV[4:0] : Clock divider of the PLL
7
6
5
4
3
2
1
0
00
7
6
5
4
3
2
1
0
01
7
6
5
4
3
2
1
0
71
7
6
5
4
3
2
DIV[4:0]
1
0
11
BYP
DIS
相關(guān)PDF資料
PDF描述
STI4600 6 CHANNEL DOLBY AC-3 MPEG1/2 AUDIO DECODER
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