參數(shù)資料
型號: STi4600
廠商: 意法半導(dǎo)體
英文描述: 6 Channel Dolby AC-3 MPEG1/2 Audio Decoder(六通道音頻解碼器)
中文描述: 6聲道杜比AC - 3 MPEG1 / 2音頻解碼器(六通道音頻解碼器)
文件頁數(shù): 18/52頁
文件大?。?/td> 321K
代理商: STI4600
18/52
STi4600
INTERNAL CIRCUIT DESCRIPTION
(Cont’d)
3.4.5.2 PCM Clock Generation
The PCM serial clock SCLK is derived from the
clock input PCMCLK. The frequency of PCMCLK
may be equal to the PCM output bit rate, or it may
be an integer multiple of this, allowing the use of
oversampling D-A converters.
SCLK is derived from PCMCLK by dividing it by
the contents of the divider register, PCM_DIV.
This number defines the ratio of the frequency of
the PCM bit clock, SCLK, to that of PCMCLK, ac-
cording the relationship:
Fsclk = F PCMCLK / (2 x (PCM_DIV+1))
The value of PCM_DIV=0 is reserved. If this
number is loaded, the divider is bypassed and the
frequency of SCLK is equal to the frequency of
PCMCLK.
The PCM_DIV register must be set up before the
output of SCLK starts. This can be done by first
disabling PCM outputs, by de-asserting the MUTE
and PLAY commands and then writing into the
PCM_DIV register. Once the register is setup, the
MUTE and/or PLAY commands can be asserted.
PCM_DIV can not be changed “on the fly”.
The frequency of LRCLK is given by:
F lrclk = Fsclk / 32 ; for 16 bit PCM output
F lrclk = F sclk /64 ; for 18, 20 or 24 bits PCM out-
put.
3.4.6 IEC output interface
The IEC output pad is a TTL output pad with slew
rate control. The output DC capability is 4 mA.The
voltage drop is 3V. This output must be connected
to a TTL driver before the transformer.
相關(guān)PDF資料
PDF描述
STI4600 6 CHANNEL DOLBY AC-3 MPEG1/2 AUDIO DECODER
STK12N06L N - Channel Enhancement Mode Low Threshold Power MOS Transistor(N溝道增強模式低閾值功率MOS晶體管)
STK12N05L N - Channel Enhancement Mode Low Threshold Power MOS Transistor(N溝道增強模式低閾值功率MOS晶體管)
STK22N05 N-Channel Enhancement Mode Power MOS Transistor(N溝道增強模式功率MOSFET)
STK22N06 N-Channel Enhancement Mode Power MOS Transistor(N溝道增強模式功率MOSFET)
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