參數(shù)資料
型號： STi4600
廠商： 意法半導(dǎo)體
英文描述： 6 Channel Dolby AC-3 MPEG1/2 Audio Decoder(六通道音頻解碼器)
中文描述： 6聲道杜比AC - 3 MPEG1 / 2音頻解碼器（六通道音頻解碼器）
文件頁數(shù)： 17/52頁
文件大小： 321K
代理商： STI4600
17/52
STi4600
INTERNAL CIRCUIT DESCRIPTION
(Cont’d)
Table 2. Data Alignments vs. PCM_PREC,
PCM_ORD, format and dif
Notations
:
{5*0} means {00000} and {4*d12} represents the
following binary word {d12,d12,d12,d12}
PCM_DIF = 1, PCM_FORMAT = 0 is compatible
with I2S format.
The polarity of the PCM serial output clock, SCLK
and LRCLK are selected by the INV_SCLK and
INV_LRCLK registers, respectively.
Figure 8 shows the two polarities of SCLK. Nor-
mally, the DAC will sample LRCLK and the PCM-
DATA on the rising edge of SCLK in the first case,
and on the falling edge of SCLK in the second.
The first option (INV_SCLK=0) is the one normally
used in I2S systems.
Figure 9 shows how the polarity of LRCLK is se-
lected. The second option (INV_LRCLK=1) is
compatible with the I2S format. See Section 4.4.5
for data output timing.
Figure 8. SCLK polarity
Figure 9. LRCLK polarity
PCM_prec
PCM_ord
format
dif
data in sample memory
data[23:0]
{d23-d8}{8*0}
{d23-d8}{8*0}
{d23-d6}{6*0}
{d23-d6}{6*0}
{d23-d6}{6*0}
{d23-d6}{6*0}
{d23-d4}{4*0}
{d23-d4}{4*0}
{d23-d4}{4*0}
{d23-d4}{4*0}
{d23-d0}
{d23-d0}
{d23-d0}
{d23-d0}
data sent on the PCM
serial output (left bit first)
{d8-d23} : 16 bits
{d23-d8} : 16 bits
{13*0}{0}{d23-d6} : 32 bits
{0}{d23-d6}{13*0} : 32 bits
{14*d23}{d23-d6} : 32 bits
{d23-d6}{14*0} : 32 bits
{11*0}{0}{d23-d4} : 32 bits
{0}{d23-d4}{11*0} : 32 bits
{12*d23}{d23-d4} : 32 bits
{d23-d4}{12*0} : 32 bits
{6*0}{0}{d23-d0} : 32 bits
{0}{d23-d0}{7*0} : 32 bits
{8*d23}{d23-d0} : 32 bits
{d23-d0}{8*0} : 32 bits
0 : 16-bit mode
0 : 16-bit mode
1 : 18-bit mode
1 : 18-bit mode
1 : 18-bit mode
1 : 18bit mode
2 : 20-bit mode
2 : 20-bit mode
2 : 20-bit mode
2 : 20-bit mode
3 : 24-bit mode
3 : 24-bit mode
3 : 24-bit mode
3 : 24-bit mode
1
0
Na
Na
0
0
1
1
0
0
1
1
0
0
1
1
Na
Na
0
1
0
1
0
1
0
1
0
1
0
1
Na
Na
Na
Na
Na
Na
Na
Na
Na
Na
Na
Na
SCLK
LRCLK,
PCM_OUT[2:0]
SCLK
LRCLK,
PCM_OUT[2:0]
INV_SCLK= 0
INV_SCLK= 1
LRCLK
INV_LRCLK= 0
INV_LRCLK= 1
left
right
left
right
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PDF描述
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