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參數(shù)資料
| 型號(hào)： | STi4600 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 6 Channel Dolby AC-3 MPEG1/2 Audio Decoder(六通道音頻解碼器) |
| 中文描述： | 6聲道杜比AC - 3 MPEG1 / 2音頻解碼器（六通道音頻解碼器） |
| 文件頁(yè)數(shù)： | 16/52頁(yè) |
| 文件大小： | 321K |
| 代理商： | STI4600 |
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STi4600
INTERNAL CIRCUIT DESCRIPTION
(Cont’d)
3.4.5 PCM OUTPUT
3.4.5.1 Interface and Output Formats
The decoded audio data are output in serial PCM
format. The interface consists of the following sig-
nals :
Output precision is selectable from 16 bits/word to
24 bits/word by setting the output precision select,
PCMCONF (16, 18, 20 and 24 bits mode), regis-
ter; see Section 5.4.3. In 16 bits mode, data may
be output either with the most significant bit first or
least significant bit first selected by the contents of
the output order select, PCMCONF.ORD. When
PCMCONF.PREC > 16 bits, 32 bits are output for
each channel. The data in front register, PCM-
CONF.DIF, is used to position the 18, 20 or 24 bits
either at the beginning or at the end of each 32-bit
frame. PCMCONF.FOR is used to select standard
or I2S-compatible format when PCM.CONF.PREC
> 16 bits is configured.
Figure 7 and Table 2 show the differents output
formats which are possible.
Figure 7. PCM Output Formats
PCM_OUT0,
PCM_OUT1,
PCM_OUT2 :
SCLK
LRCLK
PCMCLK
PCM serial data outputs
PCM clock output
Left/Right channel select output
PCM clock input
16 SCLK cycles
16 SCLK cycles
LRCLK
PCM_OUT[2:0]
PCM_OUT[2:0]
PCM_ORD = 0, PCM_PREC is 16 bits mode
M
S
L
S
M
S
M
S
M
S
L
S
L
S
L
S
LRCLK
PCM_OUT[2:0]
PCM_OUT[2:0]
PCM_OUT[2:0]
PCM_OUT[2:0]
PCM_ORD = 1, PCM_PREC is 16 bits mode
32 SCLK cycles
32 SCLK cycles
M
S
L
S
M
S
L
S
18, 20 or 24 bits
18, 20 or 24 bits
18, 20 or 24 bits
18, 20 or 24 bits
18, 20 or 24 bits
18, 20 or 24 bits
0
0
18, 20 or 24 bits
18, 20 or 24 bits
M
S
L
S
0
L
S
M
S
0
0
M
S
0
0
M
S
0
L
S
L
S
PCM_FORMAT = 1
PCM_DIFF = 1
PCM_FORMAT = 0
PCM_DIFF = 1
PCM_FORMAT = 0
PCM_DIFF = 0
PCM_FORMAT = 1
PCM_DIFF = 0
L
S
M
S
M
S
L
S
MSB
MSB
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