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參數(shù)資料
| 型號： | STi4600 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 6 Channel Dolby AC-3 MPEG1/2 Audio Decoder(六通道音頻解碼器) |
| 中文描述： | 6聲道杜比AC - 3 MPEG1 / 2音頻解碼器（六通道音頻解碼器） |
| 文件頁數(shù)： | 13/52頁 |
| 文件大?。?/td> | 321K |
| 代理商： | STI4600 |
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STi4600
INTERNAL CIRCUIT DESCRIPTION
(Cont’d)
3.4.2 Data Parallel interface
In this mode the data must be presented on the 8
bit parallel host data bus. On the rising clock of
DSTR
the data byte is sampled by the STi4600.
The signal
REQ
is used to signal when the input
FIFO is full. When
REQ
is deasserted the transfer
must be stopped to avoid to data loss.
The host data bus is shared between the Parallel
Control interface and the Data Parallel interface.
To avoid conflict the
DSTR
signal and the
CS
sig-
nal must respect certain timing constraints. The
timing diagram for the data parallel interface is giv-
en in Figure 14.
The IC can also be controlled by a host using an
I C interface or a general purpose host interface.
These interfaces provide the same functions and
are described in the following sections.
3.4.3 Parallel control interface
The address bus A[7:0] isused to select one of the
128 register locations. (A[7] is not used in the cur-
rent implementation of the devices, it can be stuck
to GND). Some registers are Read/Write, and
some write only. The signal R/W defines whether
the register access is a read or a write (high for
read, low for write).
A cycle is defined by the assertion of signal
CS
. In
response to this signal the signal
WAIT
is always
asserted. The address, read/write must be setup
before the
CS
line is activated. If a read cycle is re-
quested the data lines D[7:0] will be driven by the
IC.For a write cycle the STi4600 will latch the data
placed on the data lines on the rising edge
CS
.
The timing diagrams for the parallel control inter-
face are given in Figures 15 and 16.
3.4.4 I C control interface
3.4.4.1 Introduction :
The I C unit works at up to 400 KHz in slave mode
with 7 bit addressing. The pin MAINI2CADR se-
lects the device address. When MAINI2CADR is
high the address is0x5C, when low the device ad-
dress is equal to the value on the Data bus.
The I
C-
BUS standard does not specify sub-ad-
dressing. There are thus potentially multiple ways
to implement it. Any implementation that respects
the standard is of course legal but a particular im-
plementation is used by many companies. The fol-
lowing paragraphs describe this implementation.
3.4.4.2 Protocol Description :
For write accesses
only
, the
first data
which fol-
lows the slave address is
always
the sub-ad-
dress.This is
the one and only way
to declare the
sub-address. It should be noticed that the sub-ad-
dress is implemented as a standard data on the
I C-BUS protocol point of view.It is a sub-address
because the slave knows that it must load its ad-
dress pointer with the first data sent by the master.
Included :I
C-BUS
message format examples :
– sub-address initialization
– sub-address + single write
– sub-address + multiple write
– single read (from the current address)
– multiple read (starts from the current address)
– sub-address + single read (combined message)
– sub-address + multiple read (combined mes-
sage)
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