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參數(shù)資料
| 型號(hào)： | STi4600 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 6 Channel Dolby AC-3 MPEG1/2 Audio Decoder(六通道音頻解碼器) |
| 中文描述： | 6聲道杜比AC - 3 MPEG1 / 2音頻解碼器（六通道音頻解碼器） |
| 文件頁數(shù)： | 11/52頁 |
| 文件大?。?/td> | 321K |
| 代理商： | STI4600 |
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STi4600
INTERNAL CIRCUIT DESCRIPTION
(Cont’d)
3.4 INTERFACE DESCRIPTION
3.4.1 Data Serial interface
When serial mode is selected the STi4600 uses a
four signal data interface (see Figures 12 and 13)
that provides an input data line
SIN
, an input CLK
DSTR
, a word clock input
LRCLKIN
and a hand-
shake
output
signal
CAN_SETUP
is used to configure this serial inter-
face, see Register Manual.
3.4.1.1 Modes without LRCLKIN
In this mode thesignal LRCLKIN is not used by the
STi4600. The input data
SIN
is sampled on the ris-
ing edge of
DSTR
. When the STi4600 input buffer
is full the
REQ
signal is asserted.
The polarity of
REQ
signal is programmable. The
data must be sent most significant bits first.
When the decoder cannot accept further data the
REQ
is deasserted, the
DSTR
clock must be
stopped as soon as possible to avoid data loss. Af-
ter the
REQ
is deasserted, the decoder is still able
to accept data for a limited number of clock cycles.
The maximum number of data that can be trans-
mitted with respect to the change of
REQ
is given
by the following formula:
Nbits = 23 - 6 * FDSTRB/33MHz, Maximum value
is 23 bits, Minimum value is 17 bits.
REQ
.
The
register
Where:
FDSTR:
DSTR
clock frequency, (max is 33 MHz)
The polarity of
REQ
signal is programmable. In the
above example it is active low.The
REQ
is deas-
serted (went high on figure) asynchronously from
DSTR
. See Figure 13 for timing details.
3.4.1.2 LRCLKIN modes
These modes are used mainly for non com-
pressed data (But they can be used also for com-
pressed data). The LRCLKIN signal is used to
make the distinction between the left and right
channel. In these modes any edge of the LR-
CLKIN signal indicates a word boundary. The data
transfer between the input interface and the FIFO
is done on a byte basis. After the edge (rising or
falling) of the LRCLKIN, a new byte is transferred
to the first stage of the STi4600 every 8
DSTR
clock cycles. If the number of time slots is not a
multiple of 8, the remaining data is lost. The polar-
ity of LRCLKIN and
DSTR
are programmable. The
LRCLKIN can be delayed by one time slot, in order
to support PCM delayed mode.
The register CAN_SETUP is a 4 bit register. Each
bit has specific meaning, seeTable 1 and Register
Manual.
Table 1. CAN_SETUP Mapping
When Set
When Clear
Name
DelayMode
1
RightFirstChannel
2
FallingStrobe
4
AllSlot
8
bit[0]
The input data is one slot delayed
with respect to LRCLKIN
The input data is not delayed
bit[1]
First channel when LRCLKIN is set
First channel when LRCLKIN is clear
bit[2]
Data are sampled on falling strobe
Data are sampled on rising
strobe
bit[3]
Only the first 16 data bits are ex-
tracted
All the bytes are extracted
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