參數(shù)資料
型號: STFLWARP20
廠商: 意法半導(dǎo)體
英文描述: AB 7C 7#16S PIN RECP RoHS Compliant: No
中文描述: 8位模糊協(xié)處理器
文件頁數(shù): 13/28頁
文件大?。?/td> 275K
代理商: STFLWARP20
Register Name
Resolution
Function
Handshaking Signal Polarity
(ONLY during theOn-Line Phase)
8
0 active Low, 1 active High (default)
bit 0 READY
bit 1 RD
bit 2 WAIT
bit 3 DS
bit 4 BUSY
bit 5 LASTIN
bit 6 not connected
bit 7 START CONVERSION
000-111 = 1 to 8 Inputs
00 - 11= 1 to 4 Outputs
0 = 8 Inputs, 8 MFs per Input
1 = 4 Inputs, 16 MFs per Input
see table 4
0 = Slave Functioning
1 = Master Functioning
0000000000000-100110000100
from 0 to 2436 words to read
Number of Inputs - 1
Number of Outputs - 1
3
2
Antecedent Memory Configuration
1
A/D Conversion Pulse Width
3
On-Line Phase Master/Slave
1
Number of Wordsto load from
the External Memory
12
Note: These Registers are configurable by means of the FUZZYSTUDIO
2.0.
Table 5. RegisterBench Description.
READY
High
RD
High
WAIT
High
DS
High
BUSY
High
LASTIN
High
START C ONVERSION (O11)
High
Table 6. DefaultActive Handshaking Signal Polarity
Note: Default polarities are used in the following timing diagrams
13/28
W.A.R.P.2.0
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