- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380764 > STFLWARP20 (意法半導(dǎo)體) AB 7C 7#16S PIN RECP RoHS Compliant: No PDF資料下載
參數(shù)資料
| 型號： | STFLWARP20 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | AB 7C 7#16S PIN RECP RoHS Compliant: No |
| 中文描述： | 8位模糊協(xié)處理器 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 275K |
| 代理商： | STFLWARP20 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
0
64
16
32
48
Membership
Functions
related to
INPUT 1
Membership
Functions
related to
INPUT 2
Membership
Functions
related to
INPUT 3
Membership
Functions
related to
INPUT 4
0
1 6
8
0
0
8
MFs related
to INPUT8
MFs related
to INPUT7
MFs related
to INPUT6
MFs related
to INPUT5
MFs related
to INPUT4
MFs related
to INPUT3
MFs related
to INPUT2
MFs related
to INPUT1
64
Figure12. AntecedentMemory Spaces.
0
256 Microcode
ConsequentMFs
related to RULE 256
Microcode
ConsequentMFs
related to RULE 1
Microcode
ConsequentMFs
related to RULE 2
1
2
0
2
Number of Words to load from the external
Memory
A/D Start Conversion Pulse width
On-Line phase Master/Slave
Handshaking signals polarity
Numberof Inputs -1
Numberof Outputs -1
Antece dent Memory Configuration
3
4
1
Figure13. Program/ConsequentMemory and Register Bench.
MEMORY
There are three memories in W.A.R.P.2.0,
Antecedent Memory (AM), The Program/Conse-
quent Memory (PCM) and the Register Bench
(RB).
The AM is divided in 4 spaces, each having a
maximum of 64 bytes. It is also possible to divide
the AM in 8 parts, each having a maximum of 32
bytes.
It is possible to configure the AM in the following
modes (see fig.12):
a) up to 4 inputs, each with 16 Antecedent MFs
(MAX);
b) up to 8 inputs, each with 8 Antecedent MFs
(MAX);
Eachword (4 byte) of the AMcontains the data of
a singleMF related to an input.If W.A.R.P.2.0has
been configured to accept up to 4 inputs it is
the
possible to have up to 16 MFs for each input. If
W.A.R.P.2.0 hasbeen configuredto accept upto 8
inputs it is possible to have up to 8 MFs for each
input. Each MF of the AM contains 3 (or 2) bit
indicating to which input variable the MF is corre-
lated.
The PCM is composedby 256words (seefig. 13).
Each row (word) is related to a single rule and
contains36bitof microcodeand8bitindicatingthe
consequent MF (crisp) relatedto this rule.
The RB contains data for the configuration of the
processor that canbe set by software.
It is possibleto fix:
the number of inputs, the number of outputs, the
address of the last word to load from the external
memory, the number of MF per input, the width of
the start A/D conversion pulse, the handshaking
signals polarity and the functioning mode of the
processor (Master/Slave).
12/28
W.A.R.P.2.0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STFLWARP20PL | AB 7C 7#16S PIN RECP |
| STG8207 | Dual N-Channel E nhancement Mode F ield E ffect Transistor |
| STGB20NB41LZ | N-CHANNEL CLAMPED 20A - DPAK INTERNALLY CLAMPED PowerMESH IGBT |
| STGB20NB41LZT4 | N-CHANNEL CLAMPED 20A - DPAK INTERNALLY CLAMPED PowerMESH IGBT |
| STGD6NC60HD | N-CHANNEL 6A - 600V DPAK Very Fast PowerMESH IGBT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STFLWARP20/PL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| STFLWARP20L | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ADAPTIVE FUZZY MODELLER |
| STFLWARP20PL | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT FUZZY CO-PROCESSOR |
| STFN | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:N-CHANNEL 30V - 0.039W - 4A SOT23-6L STripFET II POWER MOSFET |
| STFN42 | 功能描述:TRANSISTOR PLANAR BIPO SOT-89 RoHS:是 類別:分離式半導(dǎo)體產(chǎn)品 >> 晶體管(BJT) - 單路 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 晶體管類型:NPN 電流 - 集電極 (Ic)（最大）:1A 電壓 - 集電極發(fā)射極擊穿（最大）:30V Ib、Ic條件下的Vce飽和度（最大）:200mV @ 100mA，1A 電流 - 集電極截止（最大）:100nA 在某 Ic、Vce 時的最小直流電流增益 (hFE):300 @ 500mA，5V 功率 - 最大:710mW 頻率 - 轉(zhuǎn)換:100MHz 安裝類型:表面貼裝 封裝/外殼:TO-236-3，SC-59，SOT-23-3 供應(yīng)商設(shè)備封裝:SOT-23-3（TO-236） 包裝:Digi-Reel® 其它名稱:MMBT489LT1GOSDKR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。