參數(shù)資料
型號(hào): ST40RA166XH6
廠商: STMICROELECTRONICS
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 166 MHz, RISC PROCESSOR, PBGA372
封裝: 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-372
文件頁(yè)數(shù): 29/92頁(yè)
文件大?。?/td> 2129K
代理商: ST40RA166XH6
5 System configuration
ST40RA
35/92
5.8.1
Memory bridge control signals
Each memory bridge has seven control signals as defined in Table 13.
5.8.2
Memory bridge status
The memory bridge control signals are looped back to the ST40RA comms subsystem SYS_STAT1
register for test purposes. The format of this read-only register is shown in Section 5.9.4.1:
5.8.3
Changing control of a memory bridge
At reset all these bridges are set to be synchronous. After reset and boot the function of these
memory bridges can be changed. See Section 5.9.4: SYSCONF registers on page 39. The
procedure for changing the control of a memory bridge is given below.
1
Ensure no initiators are accessing the subsystem the bridge is connected to and ensure the
subsystem cannot initiate any requests to the SuperHyway.
2
Stop the clock to the subsystem.
3
Change the memory bridge configuration using the SYS_CONF.SYS_CON1 register as
detailed in Table 13.
4
Restart the clock to the subsystem and reinitialize the system.
Table 13: Memory bridge control signals
Bridge control bit field
Control name
Control function
1:0
MODE[1:0]
00: Sync (bypass) bridge
01: Semisync with no retime registers
10: Semisync with one retime register
11: Async with two retime registers
4:2
LATENCY[2:0]
Sets FIFO latency from 0 to 7 cycles.
5
SW_RESET
0: Software reset inactive
1: Software reset active
6
STROBE
The above control signals are latched in the bridge on the rising
edge of this strobe bit
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