參數(shù)資料
型號(hào): ST25C08M1
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 1K X 8 SPI BUS SERIAL EEPROM, PDSO8
封裝: 0.150 INCH, PLASTIC, SO-8
文件頁(yè)數(shù): 13/16頁(yè)
文件大?。?/td> 124K
代理商: ST25C08M1
The 4 most significant bits of the device select code
are the device type identifier, corresponding to the
I2C bus definition. For these memories the 4 bits
are fixed as 1010b. The following bit identifies the
specific memory on the bus. It is matched to the
chip enable signal E. Thus up to 2 x 8K memories
can be connected on the same bus giving a mem-
ory capacity total of 16 Kbits. After a START condi-
tion any memory on the bus will identify the device
code and compare the following bit to its chip
enable input E.
The 6th and 7th bits sent, select the block number
(one block = 256 bytes). The 8th bit sent is the read
or write bit (RW), this bit is set to ’1’ for read and ’0’
for write operations. If a match is found, the corre-
sponding memory will acknowledge the identifica-
tion on the SDA bus during the 9th bit time.
Input Rise and Fall Times
≤ 50ns
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing Ref.
Voltages
0.3VCC to 0.7VCC
Table 8. AC Measurement Conditions
AI00825
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Figure 4. AC Testing Input Output Waveforms
DEVICE OPERATION (cont’d)
Symbol
Alt
Parameter
Min
Max
Unit
tCH1CH2
tR
Clock Rise Time
1
s
tCL1CL2
tF
Clock Fall Time
300
ns
tDH1DH2
tR
Input Rise Time
1
s
tDL1DL1
tF
Input Fall Time
300
ns
tCHDX
(1)
tSU:STA
Clock High to Input Transition
4.7
s
tCHCL
tHIGH
Clock Pulse Width High
4
s
tDLCL
tHD:STA
Input Low to Clock Low (START)
4
s
tCLDX
tHD:DAT
Clock Low to Input Transition
0
s
tCLCH
tLOW
Clock Pulse Width Low
4.7
s
tDXCX
tSU:DAT
Input Transition to Clock Transition
250
ns
tCHDH
tSU:STO
Clock High to Input High (STOP)
4.7
s
tDHDL
tBUF
Input High to Input Low (Bus Free)
4.7
s
tCLQV
(2)
tAA
Clock Low to Next Data Out Valid
0.3
3.5
s
tCLQX
tDH
Data Out Hold Time
300
ns
fC
fSCL
Clock Frequency
100
kHz
tW
(3)
tWR
Write Time
10
ms
Notes: 1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 addr ess MSB are not constant) the
maximum programming time is doubled to 20ms.
Table 7. AC Characteristics
(TA = 0 to 70
°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V or 2.5V to 5.5V)
6/16
ST24/25C08, ST24/25W08
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