參數(shù)資料
型號(hào)： SST26WF032-80-4I-QAE
廠商： SILICON STORAGE TECHNOLOGY INC
元件分類(lèi)： PROM
英文描述： 32M X 1 SPI BUS SERIAL EEPROM, PDSO8
封裝： 6 X 5 MM, ROHS COMPLIANT, WSON-8
文件頁(yè)數(shù)： 7/36頁(yè)
文件大小： 1339K
代理商： SST26WF032-80-4I-QAE
2010 Silicon Storage Technology, Inc.
S71409-01-000
01/10
15
1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
Reset Quad I/O (RSTQIO)
The Reset Quad I/O instruction, FFH, resets the device to 1-bit SPI protocol operation. To execute a
Reset Quad I/O operation, the host drives CE# low, sends the Reset Quad I/O command cycle (FFH)
then, drives CE# high. The device accepts either SPI (8 clocks) or SQI (2 clocks) command cycles. For
SPI, SIO[3:1] are don’t care for this command, but should be driven to VIH or VIL.
High-Speed Read (80 MHz)
The High-Speed Read instruction, 0BH, is supported in both SPI bus protocol and SQI protocol. On
power-up, the device is set to use SPI.
Initiate High-Speed Read by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and
a dummy byte. CE# must remain active low for the duration of the High-Speed Read cycle. SIO2 and
SIO3 must be driven VIH for the duration of the Read cycle. See Figure 10 for the High-Speed Read
sequence for SPI bus protocol.
Figure 10:High-Speed Read Sequence (SPI)
In SQI protocol, the host drives CE# low then send the Read command cycle command, 0BH, followed by three
address cycles and two dummy cycles. Each cycle is two nibbles (clocks) long, most significant nibble first.
After the dummy cycles, the 1.8V Serial Quad I/O (SQI) Flash Memory outputs data on the falling
edge of the SCK signal starting from the specified address location. The device continually streams
data output through all addresses until terminated by a low-to-high transition on CE#. The internal
address pointer automatically increments until the highest memory address is reached, at which point
the address pointer returns to address location 000000H.
During this operation, blocks that are Read-locked will output data 00H.
Figure 11:High-Speed Read and Read Burst Sequence (SQI)
1409 F31.0
CE#
SO/SIO1
SI/SIO0
SCK
ADD.
012 3 4 5 6 7 8
ADD.
0B
HIGH IMPEDANCE
15 16
23 24
31 32
39 40
47 48
55 56
63 64
N+2
N+3
N+4
N
N+1
X
MSB
MODE 0
MODE 3
DOUT
80
71 72
DOUT
Note: SIO2 and SIO3 must be driven VIH
Address
Dummy
Command
Data Byte 0
MSN
LSN
Data Byte 8 Data Byte 9
1409 F44.1
01
2
SCK
SIO(3:0)
CE#
C1
C0
A5
A4
A3
A2
A1
A0
X
H0
X
L0
H8
L8
H9
L9
78
11
10
913
12
19
18
21
20
MODE 3
MODE 0
34
5
6
Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble
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參數(shù)描述
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SST26WF032-80-4I-S2AE 功能描述:閃存 1.65 to 1.95V 32Mbit Serial Quad I/O Flsh RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類(lèi)型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類(lèi)型: 接口類(lèi)型:SPI 訪問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
SST26WF032-80-4I-S2AE-T 制造商:Microchip Technology Inc 功能描述:1.65 TO 1.95V 32MBIT SERIAL QUAD I/O FLASH - Tape and Reel
SST270 功能描述:JFET 45V 2mA RoHS:否 制造商:ON Semiconductor 晶體管極性:N-Channel 漏極電流（Vgs=0 時(shí)的 Idss）:50 mA 漏源電壓 VDS:15 V 閘/源擊穿電壓: 漏極連續(xù)電流:50 mA 配置: 安裝風(fēng)格: 封裝 / 箱體:SC-59 封裝:Reel
SST270-E3 功能描述:JFET 45V 2mA RoHS:否 制造商:ON Semiconductor 晶體管極性:N-Channel 漏極電流（Vgs=0 時(shí)的 Idss）:50 mA 漏源電壓 VDS:15 V 閘/源擊穿電壓: 漏極連續(xù)電流:50 mA 配置: 安裝風(fēng)格: 封裝 / 箱體:SC-59 封裝:Reel
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