參數(shù)資料
型號: SST26WF032-80-4I-QAE
廠商: SILICON STORAGE TECHNOLOGY INC
元件分類: PROM
英文描述: 32M X 1 SPI BUS SERIAL EEPROM, PDSO8
封裝: 6 X 5 MM, ROHS COMPLIANT, WSON-8
文件頁數(shù): 10/36頁
文件大?。?/td> 1339K
代理商: SST26WF032-80-4I-QAE
2010 Silicon Storage Technology, Inc.
S71409-01-000
01/10
18
1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
Figure 14:Quad J-ID Read Sequence
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4 KByte sector to ‘1,’ but it does not change
a protected memory area. Prior to any write operation, the Write-Enable (WREN) instruction must be
executed.
To execute a Sector-Erase operation, the host drives CE# low, then sends the Sector Erase command
cycle (20H) and three address cycles, and then drives CE# high. Each cycle is two nibbles, or clocks,
long, most significant nibble first. Address bits [AMS:A12] (AMS = Most Significant Address) determine
the sector address (SAX); the remaining address bits can be VIL or VIH. Poll the BUSY bit in the Status
register or wait TSE for the completion of the internal, self-timed, Sector-Erase operation. See Figure
15 for the Sector-Erase sequence.
Figure 15:4 KByte Sector-Erase Sequence
1409 F39.0
MODE 3
0
SCK
SIO(3:0)
CE#
C1 C0
MODE 0
2
H0 L0
MSN LSN
4
H1 L1
6
H2 L2
8
H0 L0
10
H1 L4
12
H2 L2
N
HN LN
BFH
N
26H
Device ID
BFH
26H
Device ID
Note: MSN = Most significant Nibble; LSN= Least Significant Nibble
C[1:0]=AFH
1409 F07.0
MODE 3
0
1
SCK
SIO(3:0)
CE#
C1 C0
MODE 0
2
A5 A4
MSN LSN
4
A3 A2
6
A1 A0
Note: MSN = Most Significant Nibble,
LSN = Least Significant Nibble
C[1:0] = 20H
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