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參數(shù)資料
| 型號： | SM8R-67025L-45/883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | SRAM |
| 英文描述： | 8K X 16 DUAL-PORT SRAM, 45 ns, CPGA84 |
| 封裝： | PGA-84 |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 257K |
| 代理商： | SM8R-67025L-45/883 |
M 67025
MATRA MHS
Rev. D (29/09/95)
12
PARAMETER
DESCRIPTION
67025–20/–25/–30/
–35/–45/–55
UNIT
VALUE
IL I/O
(5)
Input/Output leakage current
± 10
A
Max
VIL
(6)
Input low voltage
0.8
V
Max
VIH
(6)
Input high voltage
2.2
V
Min
VOL
(7)
Output low voltage (I/O0–I/O15)
0.4
V
Max
VOH
(7)
Output high voltage
2.4
V
Min
C IN
Input capacitance
5
pF
Max
C OUT
Output capacitance
7
pF
Max
Notes :
5. Vcc = 5.5 V, Vin = Gnd to Vcc, CS = VIH, Vout = 0 to Vcc.
6. VIH max = Vcc + 0.3 V, VIL min = –0.3 V or –1 V pulse width 50 ns.
7. Vcc min, IOL = 4 mA, IOH = –4 mA.
Data-Retention Mode
MHS CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure
data retention :
1 – Chip select (CS) must be held high during data
retention ; within VCC to VCC – 0.2 V.
2 – CS must be kept between VCC – 0.2 V and 70 % of VCC
during the power up and power down transitions.
3 – The RAM can begin operation > tRC after VCC
reaches the minimum operating voltage (4.5 volts).
Timing
PARAMETER (max)
TEST CONDITIONS (9)
VERSION
UNIT
PARAMETER (max)
TEST CONDITIONS (9)
V
L
UNIT
ICCDR
@ VCCDR = 2 V
Com
20
200
A
ICCDR
@ VCCDR = 2 V
Ind, Mil
200
400
A
Notes :
8. CS = VCC, Vin = Gnd to VCC.
9. tRC = Read cycle time.
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