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參數(shù)資料
| 型號： | TPS386060RGPT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQCC20 |
| 封裝： | 4 X 4 MM, PLASTIC, QFN-20 |
| 文件頁數(shù)： | 8/31頁 |
| 文件大小： | 681K |
| 代理商： | TPS386060RGPT |
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VCC
SENSE1
V
ITN
t
D
t
D
V
HYSN
0.9V
MR
RESET1
t
SBVS105B
– SEPTEMBER 2009 – REVISED MARCH 2011
RESET OUTPUT
In a typical TPS3860x0 application, RESETn or
RESETn outputs are connected to the reset input of a
processor
(DSP,
CPU,
FPGA,
ASIC,
etc.),
or
connected to the enable input of a voltage regulator
(DC-DC, LDO, etc.)
The TPS386000 and TPS386020 provide open-drain
reset outputs. Pull-up resistors must be used to hold
these lines high when RESETn is not asserted, or
when RESETn is asserted. By connecting pull-up
resistors to the proper voltage rails (up to 6.5V),
RESETn or RESETn output nodes can be connected
to the other devices at the correct interface voltage
levels. The pull-up resistor should be no smaller than
10k
because of the safe operation of the output
transistors. By using wired-OR logic, any combination
of RESETn can be merged into one logic signal.
The TPS386040 and TPS386060 provide push-pull
reset outputs. The logic high level of the outputs is
determined
by
the
VCC
voltage.
With
this
configuration, pull-up resistors are not required and
some board area can be saved. However, all the
interface
logic
levels
should
be
examined.
All
RESETn or RESETn connections must be compatible
with the VCC logic level.
The RESETn or RESETn outputs are defined for
VCC voltage higher than 0.9V. To ensure that the
target processor(s) are properly reset, the VCC
supply input should be fed by the available power rail
as early as possible in application circuits. Table 1,
Table 2, Table 3, and Table 4 are truth tables that
describe how the outputs are asserted or released.
NOTE: The TPS386000 or TPS386040 is shown here using
the SVS-n timing diagrams. When the condition(s)
RESETn. The TPS386020 and TPS386060 use RESETn;
are met, the device changes the state of SVS-n from
therefore, the diagram of RESETn should be read as RESETn with
asserted to released after a user-configurable delay
the opposite polarity.
time. However, the transitions from released-state to
Figure 26. SVS-1 Timing Diagram
asserted-state are performed almost immediately with
minimal propagation delay. Figure 28 describes
relationship between threshold voltages (VITN and
VHYSN) and SENSEm voltage; and all SVS-1, SVS-2,
SVS-3, and SVS-4 have the same behavior of
16
Copyright
2009–2011, Texas Instruments Incorporated
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