參數(shù)資料
型號: SIS300
廠商: SILICON INTEGRATED SYSTEMS CORP
元件分類: 圖形處理器
英文描述: GRAPHICS PROCESSOR, PBGA365
封裝: 27 X 27 MM, BGA-365
文件頁數(shù): 34/115頁
文件大?。?/td> 2426K
代理商: SIS300
SiS300 2D/3D/Video/DVD Accelerator
Preliminary V0.3 March 23, 1999
17
Silicon Integrated Systems Corporation
color value to three analog voltages for red, green, and blue.
2.8.8
READ-AHEAD CACHE
With read-ahead cache, the times of the operation of display memory read will be reduced,
thus enhance the performance.
2.8.9
POST WRITE BUFFER
The post write buffer contains a buffer of CPU write accesses to display memory that have
not been executed because of memory arbitration. With this buffer, the SiS300 will release
CPU as soon as it records the address and data, and then write into display memory when
the display memory is available. Thus CPU performance is increased.
2.8.10 INTERNAL TRIPLE-CLOCK SYNTHESIZER
SiS300 has built-in a triple-clock synthesizer to generate the MCLK, ECLK and VCLK. This
clock synthesizer can generate several variable frequencies, thus it can provide the flexibility
for selecting the working frequency.
The Triple-Clock Synthesizer generates MCLK, ECLK and VCLK with single external
reference clock.(14.318MHz) With this characteristic, we can set the MCLK at the maximum
speed which the display memory can work normally, thus it takes the advantage of the real
peak memory bandwidth and improves the graphics performance. And we can set the ECLK
at the maximum speed which the 3D engine can work normally, thus it takes the advantage
of the real peak 3D engine bandwidth and improves the graphics performance. The ECLK
frequency can be dynamically reduced when the 3D engine is not busy for reducing the
whole chip power consumption.
The following block diagram is for clock synthesizer.
Numerator
CP
VCO
DeNumerator
Divider
Post Scaler
fr
GAIN
+
-
fd
PD
Figure 2.8-1 Block Diagram of Clock Synthesizer
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