參數(shù)資料
型號(hào): SIS300
廠商: SILICON INTEGRATED SYSTEMS CORP
元件分類(lèi): 圖形處理器
英文描述: GRAPHICS PROCESSOR, PBGA365
封裝: 27 X 27 MM, BGA-365
文件頁(yè)數(shù): 2/115頁(yè)
文件大?。?/td> 2426K
代理商: SIS300
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SiS300 2D/3D/Video/DVD Accelerator
Preliminary V0.3 March 23, 1999
2
Silicon Integrated Systems Corporation
1.2
SiS300 FEATURES
PCI Bus Interface
Supports 32-bit PCI local bus standard Revision 2.2 compliant
Built-in write-once subsystem and subsystem-vendor ID configuration
register for on board VGA or power on auto subsystem and subsystem-
vendor ID fetching from BIOS for add-on VGA card.
Built-in PCI power management configuration register for D0, D1, D2 and D3
modes
Supports 133 MHz zero wait-state memory mapped I/O burst write
Built-in 133 MHz zero wait-state 128 bits PCI post-write buffer with byte
merge to enhance frame buffer write performance
Built-in read buffer to enhance frame buffer read performance
Supports one wait burst read cycle when read buffer hits
Supports automatic disconnect or retry after wait 16 PCI clocks when read
cache misses or post write buffer is full
Supports four wait single I/O read/write cycle
Supports full 32-bit re-locatable VGA I/O address decoding for 128 I/O ports
Supports full 32-bit memory frame buffer address decoding for 128MB size
Supports full 32-bit memory mapped I/O address decoding for 128KB size
Supports full 32-bit ROM address decoding for 32KB, 64KB sizes
Supports flash memory interface for VGA BIOS upgrade
Supports RAMDAC snoop
Supports fast back-to-back timing capable
Supports medium/slow DEVSEL decoding timing
AGP Interface
Supports AGP 2.0 compliant configuration setting
Supports AGP 2X 266 MHz with maximum 32 stages pipeline full side band
function
High Performance & High Quality 3D Accelerator
Built-in a high performance 128-bit 3D engine
- Built-in 32-bit floating point format VLIW primitive setup engine
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