參數(shù)資料
型號(hào): SIO10N268-NU
廠商: STANDARD MICROSYSTEMS CORP
元件分類(lèi): 外設(shè)及接口
英文描述: MULTIFUNCTION PERIPHERAL, PQFP128
封裝: 14 X 14 MM, 1MM THICKNESS, GREEN, TQFP-128
文件頁(yè)數(shù): 3/251頁(yè)
文件大小: 1384K
代理商: SIO10N268-NU
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Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 100
SMSC SIO10N268
DATASHEET
Bit 6
This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic "1", this bit is
equivalent to OUT1 in the MCR.
Bit 7
This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic "1", this
bit is equivalent to OUT2 in the MCR.
8.8.1.10 Scratchpad Register (SCR)
Address Offset =7H, DLAB =X, READ/WRITE
This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a
scratchpad register to be used by the programmer to hold data temporarily.
8.8.2
Programmable Baud Rate Generator (AND Divisor Latches DLH, DLL)
The Serial Ports contains a programmable Baud Rate Generator that is capable of dividing the internal
PLL clock by any divisor from 1 to 65535.
The internal PLL clock is divided down to generate a
1.8462MHz frequency for Baud Rates less than 38.4k, a 1.8432MHz frequency for 115.2k, a 3.6864MHz
frequency for 230.4k and a 7.3728MHz frequency for 460.8k. This output frequency of the Baud Rate
Generator is 16x the Baud rate. Two 8 bit latches store the divisor in 16 bit binary format. These Divisor
Latches must be loaded during initialization in order to insure desired operation of the Baud Rate
Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This
prevents long counts on initial load. If a 0 is loaded into the BRG registers the output divides the clock by
the number 3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the output
is a divide by 2 signal with a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high
for the remainder of the count. The input clock to the BRG is a 1.8462 MHz clock.
Table 8.35 shows the baud rates possible.
8.8.3
Effect Of The Reset on Register File
The Reset Function Table (Table 8.36) details the effect of the Reset input on each of the registers of the
Serial Port.
8.8.4
FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR
interrupts occur as follows:
a) The receive data available interrupt will be issued when the FIFO has reached its programmed trigger
level; it is cleared as soon as the FIFO drops below its programmed trigger level.
b) The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is
cleared when the FIFO drops below the trigger level.
c) The receiver line status interrupt (IIR=06H), has higher priority than the received data available
(IIR=04H) interrupt.
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